CAES Language for Synchronous Hardware
Haskell Other
christiaanb Fix HscTarget for ghc 8.2 and 8.6 builds
* 8.2 fails with HscNothing, so we use HscIntepreted on profiled
builds
* 8.6 is now the same as 8.4
Latest commit 82c4d9d Aug 10, 2018

README.md

CλaSH - A functional hardware description language

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CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.

Support

For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the forum