Skip to content
CAES Language for Synchronous Hardware
Branch: master
Clone or download
Latest commit 6bb4220 Apr 16, 2019
Type Name Latest commit message Commit time
Failed to load latest commit information.
.ci Test Stack build on CI Apr 10, 2019
clash-cosim @ eada464
clash-ghc Error when we're using a different clash-prelude then we were built w… Apr 9, 2019
clash-lib Add `Clash.Sized.Vector.seqV(X)` and `Clash.Sized.Vector.forceV(X)` Apr 12, 2019
doc Documentation wobble Apr 22, 2015
examples Update blinker examples to use positive resets (#559) Mar 26, 2019
tests Add `rnfX` to `Undefined` Apr 12, 2019
testsuite Add `rnfX` to `Undefined` Apr 12, 2019
.gitlab-ci.yml Test with GHC-8.6.4 Apr 2, 2019
.travis.yml Update Mar 11, 2015
cabal.project Add Generic instance for BitVector Apr 5, 2019

Clash - A functional hardware description language

Build Status Hackage Hackage Dependencies

Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of Clash:

  • Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.


For updates and questions join the mailing list or read the forum

You can’t perform that action at this time.