From 1e6b7be45e5cf0f23ed6d47b96b6fea2f8c6418a Mon Sep 17 00:00:00 2001
From: Christiaan Baaij <christiaan.baaij@gmail.com>
Date: Tue, 8 Sep 2015 09:33:55 +0200
Subject: [PATCH] Allow 'Index' type in a sum-of-product type.

Fixes #75
---
 clash-vhdl/CHANGELOG.md              | 4 ++++
 clash-vhdl/clash-vhdl.cabal          | 2 +-
 clash-vhdl/src/CLaSH/Backend/VHDL.hs | 1 +
 testsuite/Main.hs                    | 1 +
 4 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/clash-vhdl/CHANGELOG.md b/clash-vhdl/CHANGELOG.md
index dcc8657648..11873181b0 100644
--- a/clash-vhdl/CHANGELOG.md
+++ b/clash-vhdl/CHANGELOG.md
@@ -1,5 +1,9 @@
 # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package
 
+## 0.5.10
+* Fixes bugs:
+  * Maybe (Index n) not translatable to VHDL [#75](https://github.com/clash-lang/clash-compiler/issues/75)
+
 ## 0.5.9 *September 7th 2015*
 * Fixes bugs:
   * Bug in VHDL ROM generation [#69](https://github.com/clash-lang/clash-compiler/issues/69)
diff --git a/clash-vhdl/clash-vhdl.cabal b/clash-vhdl/clash-vhdl.cabal
index fb37355b98..98da34f8be 100644
--- a/clash-vhdl/clash-vhdl.cabal
+++ b/clash-vhdl/clash-vhdl.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-vhdl
-Version:              0.5.9
+Version:              0.5.10
 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
diff --git a/clash-vhdl/src/CLaSH/Backend/VHDL.hs b/clash-vhdl/src/CLaSH/Backend/VHDL.hs
index 98a025a8d5..8849ac721f 100644
--- a/clash-vhdl/src/CLaSH/Backend/VHDL.hs
+++ b/clash-vhdl/src/CLaSH/Backend/VHDL.hs
@@ -599,6 +599,7 @@ toSLV Integer      e = "std_logic_vector" <> parens ("to_signed" <> tupled (sequ
 toSLV (BitVector _) e = expr_ False e
 toSLV (Signed _)   e = "std_logic_vector" <> parens (expr_ False e)
 toSLV (Unsigned _) e = "std_logic_vector" <> parens (expr_ False e)
+toSLV (Index _)    e = "std_logic_vector" <> parens (expr_ False e)
 toSLV (Sum _ _)    e = "std_logic_vector" <> parens (expr_ False e)
 toSLV t@(Product _ tys) (Identifier id_ Nothing) = do
     selIds' <- sequence selIds
diff --git a/testsuite/Main.hs b/testsuite/Main.hs
index 6578f0f2ba..53e9e23096 100755
--- a/testsuite/Main.hs
+++ b/testsuite/Main.hs
@@ -44,6 +44,7 @@ main =
             , runTest ("tests" </> "shouldwork" </> "Basic") Both [] "Shift" (Just ("topEntity",False))
             , runTest ("tests" </> "shouldwork" </> "Basic") Both [] "SimpleConstructor" (Just ("topEntity",False))
             , runTest ("tests" </> "shouldwork" </> "Basic") Both [] "TagToEnum" (Just ("topEntity",False))
+            , runTest ("tests" </> "shouldwork" </> "Basic") Both [] "TestIndex" (Just ("topEntity",False))
             , runTest ("tests" </> "shouldwork" </> "Basic") Both [] "TwoFunctions" (Just ("topEntity",False))
             ]
         , testGroup "BitVector"