diff --git a/clash-systemverilog/primitives/CLaSH.Sized.Internal.Signed.json b/clash-systemverilog/primitives/CLaSH.Sized.Internal.Signed.json index 21eb96d00e..2538062f33 100644 --- a/clash-systemverilog/primitives/CLaSH.Sized.Internal.Signed.json +++ b/clash-systemverilog/primitives/CLaSH.Sized.Internal.Signed.json @@ -221,7 +221,7 @@ assign ~RESULT = (~SYM[1][~SIZE[~TYPO]-1] == ~SYM[2][~SIZE[~TYPO]-1]) ? "// rotateL begin logic [2*~LIT[0]-1:0] ~GENSYM[s][0]; assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2]; -assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]); +assign ~RESULT = $signed(~SYM[0][~LIT[0]-1 : 0]); // rotateL end" } } @@ -232,7 +232,7 @@ assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]); "// rotateR begin logic [2*~LIT[0]-1:0] ~GENSYM[s][0]; assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2]; -assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]); +assign ~RESULT = $signed(~SYM[0][~LIT[0]-1 : 0]); // rotateR end" } } diff --git a/clash-systemverilog/primitives/CLaSH.Sized.Internal.Unsigned.json b/clash-systemverilog/primitives/CLaSH.Sized.Internal.Unsigned.json index bc7af89ec7..aa4dcfc4b4 100644 --- a/clash-systemverilog/primitives/CLaSH.Sized.Internal.Unsigned.json +++ b/clash-systemverilog/primitives/CLaSH.Sized.Internal.Unsigned.json @@ -173,7 +173,7 @@ "// rotateL begin logic [2*~LIT[0]-1:0] ~GENSYM[u][0]; assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2]; -assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0]; +assign ~RESULT = ~SYM[0][~LIT[0]-1 : 0]; // rotateL end" } } @@ -184,7 +184,7 @@ assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0]; "// rotateR begin logic [2*~LIT[0]-1:0] ~GENSYM[u][0]; assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2]; -assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0]; +assign ~RESULT = ~SYM[0][~LIT[0]-1 : 0]; // rotateR end" } } diff --git a/clash-verilog/primitives/CLaSH.Sized.Internal.Signed.json b/clash-verilog/primitives/CLaSH.Sized.Internal.Signed.json index d512f99650..70a1994ab9 100644 --- a/clash-verilog/primitives/CLaSH.Sized.Internal.Signed.json +++ b/clash-verilog/primitives/CLaSH.Sized.Internal.Signed.json @@ -221,7 +221,7 @@ assign ~RESULT = (~SYM[1][~SIZE[~TYPO]-1] == ~SYM[2][~SIZE[~TYPO]-1]) ? "// rotateL begin wire [2*~LIT[0]-1:0] ~SYM[0]; assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2]; -assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]); +assign ~RESULT = $signed(~SYM[0][~LIT[0]-1 : 0]); // rotateL end" } } @@ -232,7 +232,7 @@ assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]); "// rotateR begin wire [2*~LIT[0]-1:0] ~GENSYM[s][0]; assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2]; -assign ~RESULT = $signed(~SYM[0][~LIT[1]-1 : 0]); +assign ~RESULT = $signed(~SYM[0][~LIT[0]-1 : 0]); // rotateR end" } } diff --git a/clash-verilog/primitives/CLaSH.Sized.Internal.Unsigned.json b/clash-verilog/primitives/CLaSH.Sized.Internal.Unsigned.json index 52c367fd2a..83f3d0184a 100644 --- a/clash-verilog/primitives/CLaSH.Sized.Internal.Unsigned.json +++ b/clash-verilog/primitives/CLaSH.Sized.Internal.Unsigned.json @@ -173,7 +173,7 @@ "// rotateL begin wire [2*~LIT[0]-1:0] ~GENSYM[u][0]; assign ~SYM[0] = {~ARG[1],~ARG[1]} << ~ARG[2]; -assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0]; +assign ~RESULT = ~SYM[0][~LIT[0]-1 : 0]; // rotateL end" } } @@ -184,7 +184,7 @@ assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0]; "// rotateR begin wire [2*~LIT[0]-1:0] ~GENSYM[u][0]; assign ~SYM[0] = {~ARG[1],~ARG[1]} >> ~ARG[2]; -assign ~RESULT = ~SYM[0][~LIT[1]-1 : 0]; +assign ~RESULT = ~SYM[0][~LIT[0]-1 : 0]; // rotateR end" } } diff --git a/tests/shouldwork/Basic/NORX.hs b/tests/shouldwork/Basic/NORX.hs new file mode 100644 index 0000000000..bcb1acfd13 --- /dev/null +++ b/tests/shouldwork/Basic/NORX.hs @@ -0,0 +1,69 @@ +module NORX where +import Data.Bits +import CLaSH.Prelude + +type W = Unsigned 32 + +norx :: Vec 16 W -> Vec 16 W +norx inp = iterate d5 f inp !! 4 + +f :: Vec 16 W -> Vec 16 W +f inp = result + where + (s0:>s1:>s2:>s3:>s4:>s5:>s6:>s7:>s8:>s9:>s10:>s11:>s12:>s13:>s14:>s15:>_) = inp + + -- Column round + (t0, t4, t8, t12) = g (s0, s4, s8, s12) + (t1, t5, t9, t13) = g (s1, s5, s9, s13) + (t2, t6, t10, t14) = g (s2, s6, s10, s14) + (t3, t7, t11, t15) = g (s3, s7, s11, s15) + -- Diagonal round + (u0, u5, u10, u15) = g (t0, t5, t10, t15) + (u1, u6, u11, u12) = g (t1, t6, t11, t12) + (u2, u7, u8, u13) = g (t2, t7, t8, t13) + (u3, u4, u9, u14) = g (t3, t4, t9, t14) + + result = (u0:>u1:>u2:>u3:>u4:>u5:>u6:>u7:>u8:>u9:>u10:>u11:>u12:>u13:>u14:>u15:>Nil) + +g :: (W, W, W, W) -> (W, W, W, W) +g (a, b, c, d) = (a'', b'', c'', d'') + where + a' = h a b + d' = (a' `xor` d) `rotateR` 8 + c' = h c d' + b' = (b `xor` c') `rotateR` 11 + a'' = h a' b' + d'' = (a'' `xor` d') `rotateR` 16 + c'' = h c' d'' + b'' = (b' `xor` c'') `rotateR` 31 + +h :: W -> W -> W +h x y = (x `xor` y) `xor` ((x .&. y) `shiftL` 1) + +-------------------------------------------------------------------------------- +-- HDL export interface + +topEntity :: Vec 16 W -> Vec 16 W +topEntity = norx + +testInput :: Signal (Vec 16 (Unsigned 32)) +testInput = stimuliGenerator $(v [ (0 :: Unsigned 32):>1:>2:>3:>4:>5:>6:>7:>8:>9:>10:>11:>12:>13:>14:>15:>Nil ] ) + +expectedOutput :: Signal (Vec 16 (Unsigned 32)) -> Signal Bool +expectedOutput = outputVerifier $(v [ (0x99a0283a :: Unsigned 32) + :> 0x16c4b42e + :> 0x6e7fa00b + :> 0x7d075c66 + :> 0x65c1af81 + :> 0xee254c00 + :> 0x126631b6 + :> 0xf8915260 + :> 0x083181d5 + :> 0x85dc0152 + :> 0x1a44a1f3 + :> 0x7ba61b1a + :> 0x37dde5df + :> 0x078203d3 + :> 0x9b3c0701 + :> 0x9ce6be37 + :> Nil ]) diff --git a/testsuite/Main.hs b/testsuite/Main.hs index a955de134a..ab625f4f05 100755 --- a/testsuite/Main.hs +++ b/testsuite/Main.hs @@ -44,6 +44,7 @@ main = , runTest ("tests" "shouldwork" "Basic") Both [] "IrrefError" (Just ("topEntity",False)) , runTest ("tests" "shouldwork" "Basic") Both [] "NestedPrimitives" (Just ("topEntity",False)) , runTest ("tests" "shouldwork" "Basic") Both [] "NestedPrimitives2" (Just ("topEntity",False)) + , runTest ("tests" "shouldwork" "Basic") Both [] "NORX" (Just ("testbench",True)) , runTest ("tests" "shouldwork" "Basic") Both [] "PatError" (Just ("topEntity",False)) , runTest ("tests" "shouldwork" "Basic") Both [] "PopCount" (Just ("testbench",True)) , runTest ("tests" "shouldwork" "Basic") Both [] "RecordSumOfProducts" (Just ("topEntity",False))