diff --git a/clash-systemverilog/src/CLaSH/Backend/SystemVerilog.hs b/clash-systemverilog/src/CLaSH/Backend/SystemVerilog.hs
index 85ca7fe254..b8d646f794 100644
--- a/clash-systemverilog/src/CLaSH/Backend/SystemVerilog.hs
+++ b/clash-systemverilog/src/CLaSH/Backend/SystemVerilog.hs
@@ -724,7 +724,7 @@ expr_ _ (DataCon ty@(SP _ args) (DC (_,i)) es) = assignExpr
     argExprs   = zipWith toSLV argTys es
     extraArg   = case typeSize ty - dcSize of
                    0 -> []
-                   n -> [exprLit (Just (ty,n)) (NumLit 0)]
+                   n -> [int n <> "'b" <> bits (replicate n U)]
     assignExpr = braces (hcat $ punctuate comma $ sequence (dcExpr:argExprs ++ extraArg))
 
 expr_ _ (DataCon ty@(Sum _ _) (DC (_,i)) []) = int (typeSize ty) <> "'d" <> int i
diff --git a/clash-verilog/src/CLaSH/Backend/Verilog.hs b/clash-verilog/src/CLaSH/Backend/Verilog.hs
index 31b57c27cd..06e3f25dbb 100644
--- a/clash-verilog/src/CLaSH/Backend/Verilog.hs
+++ b/clash-verilog/src/CLaSH/Backend/Verilog.hs
@@ -383,7 +383,7 @@ expr_ _ (DataCon ty@(SP _ args) (DC (_,i)) es) = assignExpr
     argExprs   = map (expr_ False) es
     extraArg   = case typeSize ty - dcSize of
                    0 -> []
-                   n -> [exprLit (Just (ty,n)) (NumLit 0)]
+                   n -> [int n <> "'b" <> bits (replicate n U)]
     assignExpr = braces (hcat $ punctuate comma $ sequence (dcExpr:argExprs ++ extraArg))
 
 expr_ _ (DataCon ty@(Sum _ _) (DC (_,i)) []) = int (typeSize ty) <> "'d" <> int i
diff --git a/clash-vhdl/src/CLaSH/Backend/VHDL.hs b/clash-vhdl/src/CLaSH/Backend/VHDL.hs
index 9350511f89..12469d99fe 100644
--- a/clash-vhdl/src/CLaSH/Backend/VHDL.hs
+++ b/clash-vhdl/src/CLaSH/Backend/VHDL.hs
@@ -737,7 +737,7 @@ expr_ _ (DataCon ty@(SP _ args) (DC (_,i)) es) = assignExpr
     argExprs   = zipWith toSLV argTys es
     extraArg   = case typeSize ty - dcSize of
                    0 -> []
-                   n -> [exprLit (Just (ty,n)) (NumLit 0)]
+                   n -> [bits (replicate n U)]
     assignExpr = "std_logic_vector'" <> parens (hcat $ punctuate " & " $ sequence (dcExpr:argExprs ++ extraArg))
 
 expr_ _ (DataCon ty@(Sum _ _) (DC (_,i)) []) = "to_unsigned" <> tupled (sequence [int i,int (typeSize ty)])