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Verilog ModInteger primitive results into a syntax error in modelSim #164

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vzaccaria opened this Issue Jul 29, 2016 · 1 comment

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@vzaccaria

vzaccaria commented Jul 29, 2016

This line seems the culprit:

                 ((~ARG[1] == ~SIZE[~TYPO]'sd0 ? ~SIZE[~TYPO]'sd0) : ~SYM[0] + ~ARG[1]);

Should instead be

                 ((~ARG[1] == ~SIZE[~TYPO]'sd0) ? ~SIZE[~TYPO]'sd0 : ~SYM[0] + ~ARG[1]);

?

@christiaanb

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christiaanb Jul 29, 2016

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Yes, your fix seems to be right. I'll fix it after the weekend. As a work-around you can create your own primitive definition as described here: http://hackage.haskell.org/package/clash-prelude-0.10.10/docs/CLaSH-Tutorial.html#g:14

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christiaanb commented Jul 29, 2016

Yes, your fix seems to be right. I'll fix it after the weekend. As a work-around you can create your own primitive definition as described here: http://hackage.haskell.org/package/clash-prelude-0.10.10/docs/CLaSH-Tutorial.html#g:14

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