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-- Automatically generated VHDL-93library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.reseteither_types.all;
entityResetEitherisport(-- asynchronous reset: active high
A_RST : instd_logic;
-- asynchronous reset: active high
B_RST : instd_logic;
-- asynchronous reset: active high
RST_OUT : outstd_logic);
end;
architecturestructuralofResetEitherissignal ds1 : boolean;
signal result : boolean;
signal ds1_0 : boolean;
signal result_0 : boolean;
begin
ds1 <=truewhen A_RST ='1'elsefalse;
result <=falsewhen ds1 elsetrue;
ds1_0 <=truewhen B_RST ='1'elsefalse;
result_0 <=falsewhen ds1_0 elsetrue;
RST_OUT <='1'when (result or result_0) else'0';
end;
Now, if I were to change the following lines in my source Haskell code from:
andA = ((.==.) (pureFalse) rstaBool)
andB = ((.==.) (pureFalse) rstbBool)
Where I use bitToBool to create my first Bool value and 'rst_val' is a Bit type that is equal to '0'. The functionality remains the same, however the following VHDL is generated instead:
-- Automatically generated VHDL-93library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.reseteither_types.all;
entityResetEitherisport(-- asynchronous reset: active high
A_RST : instd_logic;
-- asynchronous reset: active high
B_RST : instd_logic;
-- asynchronous reset: active high
RST_OUT : outstd_logic);
end;
architecturestructuralofResetEitherissignal\#case_alt\ : boolean;
signal ds1 : boolean;
signal result : boolean;
signal\#case_alt_0\ : boolean;
signal ds1_0 : boolean;
signal result_0 : boolean;
signal result_selection_res : std_logic_vector(0downto0);
signal\#i\ : signed(63downto0);
signal result_0_selection_res : std_logic_vector(0downto0);
signal\#i_0\ : signed(63downto0);
begin\#case_alt\<=falsewhen ds1 elsetrue;
ds1 <=truewhen A_RST ='1'elsefalse;
\#i\<=to_signed(0,64);
result_selection_res <=std_logic_vector'(0=>'0');
with (result_selection_res) select
result <= ds1 when"1",
\#case_alt\whenothers;
\#case_alt_0\<=falsewhen ds1_0 elsetrue;
ds1_0 <=truewhen B_RST ='1'elsefalse;
\#i_0\<=to_signed(0,64);
result_0_selection_res <=std_logic_vector'(0=>'0');
with (result_0_selection_res) select
result_0 <= ds1_0 when"1",
\#case_alt_0\whenothers;
RST_OUT <='1'when (result or result_0) else'0';
end;
As, you can see, there are several instances where the compiler generated signed 64 bit integers in the VHDL that are not being used (signals #i\ and #i_0). Has anyone else had similar issues with the 'boolToBit' or 'bittoBool' functions found in Clash.Class.BitPack ?
I would prefer to have each signal be of Bit type rather than Bool for my particular application. But this issue tends to bloat the VHDL signal declarations on my other larger designs that use 'bitToBool' more often.
The text was updated successfully, but these errors were encountered:
Nrmize
changed the title
CLaSH compiler generates unused signed integers when doing a Bit comparison
CLaSH compiler generates unused signed integers when converting from type Bit to Bool
Jul 19, 2018
Hi all,
I noticed something peculiar in a piece of code that I made to combine and invert two reset signals into one. Here is the code block I made:
This code will generate the following VHDL:
Now, if I were to change the following lines in my source Haskell code from:
To:
Where I use bitToBool to create my first Bool value and 'rst_val' is a Bit type that is equal to '0'. The functionality remains the same, however the following VHDL is generated instead:
As, you can see, there are several instances where the compiler generated signed 64 bit integers in the VHDL that are not being used (signals #i\ and #i_0). Has anyone else had similar issues with the 'boolToBit' or 'bittoBool' functions found in Clash.Class.BitPack ?
I would prefer to have each signal be of Bit type rather than Bool for my particular application. But this issue tends to bloat the VHDL signal declarations on my other larger designs that use 'bitToBool' more often.
The text was updated successfully, but these errors were encountered: