From 7e10db358b4128b0550b4150826f32eefdd49d13 Mon Sep 17 00:00:00 2001
From: Jerg Kappeler <jerg.kappeler@tum.de>
Date: Mon, 8 Sep 2025 16:17:46 +0200
Subject: [PATCH 1/2] reset the default_nettype to wire at the end of the
 generated verilog file

---
 changelog/2025-09-05T19_03_39+02_00_implicit_nets | 1 +
 clash-lib/src/Clash/Backend/SystemVerilog.hs      | 9 ++++++---
 clash-lib/src/Clash/Backend/Verilog.hs            | 9 +++++++--
 3 files changed, 14 insertions(+), 5 deletions(-)
 create mode 100644 changelog/2025-09-05T19_03_39+02_00_implicit_nets

diff --git a/changelog/2025-09-05T19_03_39+02_00_implicit_nets b/changelog/2025-09-05T19_03_39+02_00_implicit_nets
new file mode 100644
index 0000000000..183f703c2c
--- /dev/null
+++ b/changelog/2025-09-05T19_03_39+02_00_implicit_nets
@@ -0,0 +1 @@
+CHANGED: when generating (System)Verilog, Clash now resets the default net type from none to the verilog default after the generated module
diff --git a/clash-lib/src/Clash/Backend/SystemVerilog.hs b/clash-lib/src/Clash/Backend/SystemVerilog.hs
index ca2be36a6d..cb42d2c2f8 100644
--- a/clash-lib/src/Clash/Backend/SystemVerilog.hs
+++ b/clash-lib/src/Clash/Backend/SystemVerilog.hs
@@ -228,14 +228,17 @@ genSystemVerilog opts _ sp seen us c = do
   where
     cName   = componentName c
     verilog = commentHeader <> line <>
-              nettype <> line <>
+              nettypeNone <> line <>
               timescale <> line <>
-              module_ c
+              module_ c <> line <>
+              nettypeDefault 
+
     commentHeader
          = "/* AUTOMATICALLY GENERATED SYSTEMVERILOG-2005 SOURCE CODE."
       <> line <> "** GENERATED BY CLASH " <> string (Text.pack clashVer) <> ". DO NOT MODIFY."
       <> line <> "*/"
-    nettype = "`default_nettype none"
+    nettypeNone = "`default_nettype none"
+    nettypeDefault = "`default_nettype wire"
     timescale = "`timescale 100fs/" <> string (Text.pack precision)
     precision = periodToString (opt_timescalePrecision opts)
 
diff --git a/clash-lib/src/Clash/Backend/Verilog.hs b/clash-lib/src/Clash/Backend/Verilog.hs
index 26b77f1257..a74f56807d 100644
--- a/clash-lib/src/Clash/Backend/Verilog.hs
+++ b/clash-lib/src/Clash/Backend/Verilog.hs
@@ -225,7 +225,11 @@ genVerilog opts  _ sp seen usage c = do
       usages .= usage
       setSrcSpan sp
 
-    v    <- commentHeader <> line <> nettype <> line <> timescale <> line <> module_ c
+    v    <- commentHeader <> line <>
+            nettypeNone <> line <>
+            timescale <> line <>
+            module_ c <> line <>
+            nettypeDefault
     incs <- Ap $ use includes
     return ((TextS.unpack (Id.toText cName), v), incs)
   where
@@ -234,7 +238,8 @@ genVerilog opts  _ sp seen usage c = do
          = "/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE."
       <> line <> "** GENERATED BY CLASH " <> string (Text.pack clashVer) <> ". DO NOT MODIFY."
       <> line <> "*/"
-    nettype = "`default_nettype none"
+    nettypeNone = "`default_nettype none"
+    nettypeDefault = "`default_nettype wire"
     timescale = "`timescale 100fs/" <> string (Text.pack precision)
     precision = periodToString (opt_timescalePrecision opts)
 

From 3d679ae8f41d0bed22cacc7dac932b49ee79e4b8 Mon Sep 17 00:00:00 2001
From: Jerg Kappeler <jerg.kappeler@tum.de>
Date: Tue, 9 Sep 2025 12:49:44 +0200
Subject: [PATCH 2/2] fix: remove trailing whitespace

---
 clash-lib/src/Clash/Backend/SystemVerilog.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clash-lib/src/Clash/Backend/SystemVerilog.hs b/clash-lib/src/Clash/Backend/SystemVerilog.hs
index cb42d2c2f8..1e227f85dc 100644
--- a/clash-lib/src/Clash/Backend/SystemVerilog.hs
+++ b/clash-lib/src/Clash/Backend/SystemVerilog.hs
@@ -231,7 +231,7 @@ genSystemVerilog opts _ sp seen us c = do
               nettypeNone <> line <>
               timescale <> line <>
               module_ c <> line <>
-              nettypeDefault 
+              nettypeDefault
 
     commentHeader
          = "/* AUTOMATICALLY GENERATED SYSTEMVERILOG-2005 SOURCE CODE."