251 Lab2.fit.rpt
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4 Lab2.fit.summary
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@@ -1,4 +1,4 @@
Fitter Status : Successful - Thu Feb 19 01:16:13 2015
Fitter Status : Successful - Thu Feb 19 17:46:56 2015
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : Lab2
Top-level Entity Name : Lab2
@@ -9,7 +9,7 @@ Total logic elements : 0 / 14,400 ( 0 % )
Total combinational functions : 0 / 14,400 ( 0 % )
Dedicated logic registers : 0 / 14,400 ( 0 % )
Total registers : 0
Total pins : 37 / 81 ( 46 % )
Total pins : 36 / 81 ( 44 % )
Total virtual pins : 0
Total memory bits : 0 / 552,960 ( 0 % )
Embedded Multiplier 9-bit elements : 0
20 Lab2.flow.rpt
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@@ -1,5 +1,5 @@
Flow report for Lab2
Thu Feb 19 01:16:21 2015
Thu Feb 19 17:47:03 2015
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


@@ -40,7 +40,7 @@ applicable agreement for further details.
+--------------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Thu Feb 19 01:16:17 2015 ;
; Flow Status ; Successful - Thu Feb 19 17:47:00 2015 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; Lab2 ;
; Top-level Entity Name ; Lab2 ;
@@ -49,7 +49,7 @@ applicable agreement for further details.
; Total combinational functions ; 0 / 14,400 ( 0 % ) ;
; Dedicated logic registers ; 0 / 14,400 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 37 / 81 ( 46 % ) ;
; Total pins ; 36 / 81 ( 44 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 552,960 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 ;
@@ -68,7 +68,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 02/19/2015 01:16:04 ;
; Start date & time ; 02/19/2015 17:46:48 ;
; Main task ; Compilation ;
; Revision Name ; Lab2 ;
+-------------------+---------------------+
@@ -79,7 +79,7 @@ applicable agreement for further details.
+-------------------------------------+---------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+---------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 154414184164089.142433736406256 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 154414184164089.142439680806840 ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
@@ -91,11 +91,11 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 493 MB ; 00:00:01 ;
; Fitter ; 00:00:07 ; 1.0 ; 705 MB ; 00:00:07 ;
; Assembler ; 00:00:01 ; 1.0 ; 472 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 453 MB ; 00:00:03 ;
; Total ; 00:00:13 ; -- ; -- ; 00:00:13 ;
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 493 MB ; 00:00:01 ;
; Fitter ; 00:00:06 ; 1.0 ; 709 MB ; 00:00:06 ;
; Assembler ; 00:00:02 ; 1.0 ; 468 MB ; 00:00:01 ;
; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 453 MB ; 00:00:02 ;
; Total ; 00:00:11 ; -- ; -- ; 00:00:10 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+


2 Lab2.jdi
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@@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="0d9492a14796966a674f"/>
<hash md5_digest_80b="cb6cf3500160563ab3e8"/>
</project>
<file_info>
<file device="EP4CGX15BF14C6" path="Lab2.sof" usercode="0xFFFFFFFF"/>
30 Lab2.map.rpt
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@@ -1,5 +1,5 @@
Analysis & Synthesis report for Lab2
Thu Feb 19 01:16:05 2015
Thu Feb 19 17:46:49 2015
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


@@ -41,7 +41,7 @@ applicable agreement for further details.
+--------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Feb 19 01:16:05 2015 ;
; Analysis & Synthesis Status ; Successful - Thu Feb 19 17:46:49 2015 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; Lab2 ;
; Top-level Entity Name ; Lab2 ;
@@ -50,7 +50,7 @@ applicable agreement for further details.
; Total combinational functions ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 37 ;
; Total pins ; 36 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
@@ -178,11 +178,11 @@ Parallel compilation was disabled, but you have multiple processors available. E
+--------------------------+------------------+
; Resource ; Usage ;
+--------------------------+------------------+
; I/O pins ; 37 ;
; I/O pins ; 36 ;
; DSP block 9-bit elements ; 0 ;
; Maximum fan-out node ; currentPC~output ;
; Maximum fan-out ; 1 ;
; Total fan-out ; 37 ;
; Total fan-out ; 36 ;
; Average fan-out ; 0.50 ;
+--------------------------+------------------+

@@ -192,7 +192,7 @@ Parallel compilation was disabled, but you have multiple processors available. E
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |Lab2 ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 37 ; 0 ; |Lab2 ; work ;
; |Lab2 ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 36 ; 0 ; |Lab2 ; work ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.

@@ -227,7 +227,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Feb 19 01:16:03 2015
Info: Processing started: Thu Feb 19 17:46:48 2015
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Lab2 -c Lab2
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file control.sv
@@ -239,6 +239,8 @@ Warning (275043): Pin "currentPC" is missing source
Warning (12125): Using design file regfile.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: regfile
Info (12128): Elaborating entity "regfile" for hierarchy "regfile:inst"
Info (12128): Elaborating entity "control" for hierarchy "control:inst2"
Warning (10270): Verilog HDL Case Statement warning at control.sv(40): incomplete case statement has no default case item
Warning (12125): Using design file instr_rom.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: instr_rom
Info (12128): Elaborating entity "instr_rom" for hierarchy "instr_rom:inst3"
@@ -260,14 +262,12 @@ Warning (10230): Verilog HDL assignment warning at alu.sv(37): truncated value w
Warning (10230): Verilog HDL assignment warning at alu.sv(38): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at alu.sv(39): truncated value with size 32 to match size of target (1)
Warning (10958): SystemVerilog warning at alu.sv(27): unique or priority keyword makes case statement complete
Info (12128): Elaborating entity "control" for hierarchy "control:inst2"
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "currentPC" is stuck at GND
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 36 input pin(s) that do not drive logic
Warning (21074): Design contains 35 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "clk"
Warning (15610): No output dependent on input pin "clkFetch"
Warning (15610): No output dependent on input pin "start"
Warning (15610): No output dependent on input pin "branchFetch"
Warning (15610): No output dependent on input pin "branchloc[15]"
@@ -302,13 +302,13 @@ Warning (21074): Design contains 36 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "start_address[2]"
Warning (15610): No output dependent on input pin "start_address[1]"
Warning (15610): No output dependent on input pin "start_address[0]"
Info (21057): Implemented 37 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 36 input pins
Info (21057): Implemented 36 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 35 input pins
Info (21059): Implemented 1 output pins
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 57 warnings
Info: Peak virtual memory: 504 megabytes
Info: Processing ended: Thu Feb 19 01:16:05 2015
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
Info: Processing ended: Thu Feb 19 17:46:49 2015
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01


4 Lab2.map.summary
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@@ -1,4 +1,4 @@
Analysis & Synthesis Status : Successful - Thu Feb 19 01:16:05 2015
Analysis & Synthesis Status : Successful - Thu Feb 19 17:46:49 2015
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : Lab2
Top-level Entity Name : Lab2
@@ -7,7 +7,7 @@ Total logic elements : 0
Total combinational functions : 0
Dedicated logic registers : 0
Total registers : 0
Total pins : 37
Total pins : 36
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
88 Lab2.pin
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BIN +0 Bytes (100%) Lab2.sof
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11 Lab2.sta.rpt
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@@ -1,5 +1,5 @@
TimeQuest Timing Analyzer report for Lab2
Thu Feb 19 01:16:21 2015
Thu Feb 19 17:47:03 2015
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


@@ -268,7 +268,6 @@ No synchronizer chains to report.
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------+--------------+-----------------+-----------------+
; clk ; 2.5 V ; 2000 ps ; 2000 ps ;
; clkFetch ; 2.5 V ; 2000 ps ; 2000 ps ;
; start ; 2.5 V ; 2000 ps ; 2000 ps ;
; branchFetch ; 2.5 V ; 2000 ps ; 2000 ps ;
; branchloc[15] ; 2.5 V ; 2000 ps ; 2000 ps ;
@@ -380,7 +379,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Thu Feb 19 01:16:18 2015
Info: Processing started: Thu Feb 19 17:47:01 2015
Info: Command: quartus_sta Lab2 -c Lab2
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
@@ -428,8 +427,8 @@ Info (332101): Design is fully constrained for setup requirements
Info (332101): Design is fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 453 megabytes
Info: Processing ended: Thu Feb 19 01:16:21 2015
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:03
Info: Processing ended: Thu Feb 19 17:47:03 2015
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02


7 control.bsf
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@@ -51,6 +51,13 @@ applicable agreement for further details.
(text "alu_inst[3..0]" (rect 130 27 179 39)(font "Arial" ))
(line (pt 200 32)(pt 184 32)(line_width 3))
)
(port
(pt 200 48)
(output)
(text "write_flag" (rect 0 0 37 12)(font "Arial" ))
(text "write_flag" (rect 142 43 179 55)(font "Arial" ))
(line (pt 200 48)(pt 184 48)(line_width 1))
)
(drawing
(rectangle (rect 16 16 184 96)(line_width 1))
)
20 control.sv
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@@ -29,31 +29,37 @@ module control(
input [1:0]format,
input imm_flag,
input [3:0]opcode,
output reg [3:0]alu_inst
output reg [3:0]alu_inst,
output reg write_flag
);


always_comb begin
write_flag = 0;
alu_inst[3:0] = 4'bxxxx;
case(opcode)
`ADD_OP: alu_inst[3:0] = `ALUOP_ADD;
`SUB_OP: alu_inst[3:0] = `ALUOP_SUB;
`ADD_OP: alu_inst[3:0] = `ALUOP_ADD;
`SUB_OP: alu_inst[3:0] = `ALUOP_SUB;
`SFT_OP: begin
if(imm_flag)
alu_inst[3:0] = `ALUOP_SFR;
else
alu_inst[3:0] = `ALUOP_SFL;
end
`BNE_OP: alu_inst[3:0] = `ALUOP_BNE;
`BEQ_OP: alu_inst[3:0] = `ALUOP_BEQ;
`BLT_OP: alu_inst[3:0] = `ALUOP_BLT;
`BEQ_OP: alu_inst[3:0] = `ALUOP_BEQ;
`BLT_OP: alu_inst[3:0] = `ALUOP_BLT;
`INC_OP: begin
if(imm_flag)
alu_inst[3:0] = `ALUOP_INC;
else
alu_inst[3:0] = `ALUOP_DEC;
end
default: alu_inst[3:0] = 4'bxxxx;
/*`LB_OP:
`LB_OP: begin
write_flag = 1;
alu_inst[3:0] = 4'bxxxx;
end
/*
`LHB_OP:
`JMP_OP:
`STR_OP: