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How to implement register file to block RAM manually? #30
Hmm. This is a strange limitation. What architecture/toolchain is that?
I see two options:
Option 1: Use Yosys to synthesize the pivorv32 verilog code into lower-level verilog with the register file mapped to a block ram. I.e. do something like this:
This will create a
You have to provide an implementation of this module, which can be a simple wrapper for your block rams. A1 and A2 are the read ports, B1 is the write port.
The following (untested) code demonstrates the semantics of the
If you enable interrupts with Q registers then you'll have to change
If you set
Option 2: Refactor the
This is the relevant code from
Note that this code does not contain any read FFs. If you only have block RAMS with read FFs then manually refactoring the code to use them explicitly might be hard and option 1 becomes much more interesting.
rgwan@laptop:~/anlogic/picorv32_demo$ vvp tb
Hellb Jbeld! If lbh caa eead ghif meffage ghea
(BTW, these options I have enabled in origin file)
(I've fixed a typo in my verilog code above:
I've now added a complete example for this:
Seems to be working fine here:
The register code listed above:
That shows the read data is registered so it shows up after the rising edge of CLK1.