From 1fd8c0a3225500599b873f0ab364076781f87d22 Mon Sep 17 00:00:00 2001 From: Lukas Date: Tue, 3 Feb 2015 20:49:42 +0100 Subject: [PATCH 1/6] new werkflows to validated digi-reco pu mixing in fastsim --- .../PyReleaseValidation/python/relval_pileup.py | 8 ++++++-- .../PyReleaseValidation/python/relval_steps.py | 12 +++++++++--- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/Configuration/PyReleaseValidation/python/relval_pileup.py b/Configuration/PyReleaseValidation/python/relval_pileup.py index d0c3b2bbaefc8..d937c63c8f80a 100644 --- a/Configuration/PyReleaseValidation/python/relval_pileup.py +++ b/Configuration/PyReleaseValidation/python/relval_pileup.py @@ -45,7 +45,11 @@ workflows[25204]=['',['QQH1352T_13','DIGIUP15_PU25','RECOUP15_PU25','HARVESTUP15','MINIAODMCUP15']] workflows[25205]=['',['ZTT_13','DIGIUP15_PU25','RECOUP15_PU25','HARVESTUP15','MINIAODMCUP15']] workflows[25206]=['',['ZMM_13','DIGIUP15_PU25','RECOUP15_PU25','HARVESTUP15','MINIAODMCUP15']] +workflows[25207]=['',['NuGun_UP15','DIGIUP15_PU25','RECOUP15_PU25','HARVESTUP15','MINIAODMCUP15']] #fastsim -workflows[25400]=['TTbar_13_AVE10',['TTbarFSPU13AVE10','HARVESTUP15FS','MINIAODMCUP15FS']] -workflows[25401]=['TTbar_13_AVE20',['TTbarFSPU13AVE20','HARVESTUP15FS','MINIAODMCUP15FS']] +workflows[25400]=['',['FS_TTbar_13_PUAVE10','HARVESTUP15FS','MINIAODMCUP15FS']] +workflows[25400.1]=['',['FS_TTbar_13_PUAVE10_DIGIRECOMIX_ITO','HARVESTUP15FS','MINIAODMCUP15FS']] +workflows[25401]=['',['FS_TTbar_13_PUAVE20','HARVESTUP15FS','MINIAODMCUP15FS']] +workflows[25402]=['',['FS_TTbar_13_PU25','HARVESTUP15FS','MINIAODMCUP15FS']] +workflows[25407]=['',['FS_NuGun_UP15_PU25','HARVESTUP15FS','MINIAODMCUP15FS']] diff --git a/Configuration/PyReleaseValidation/python/relval_steps.py b/Configuration/PyReleaseValidation/python/relval_steps.py index 6d79ecdea47c0..0228c63755ddd 100644 --- a/Configuration/PyReleaseValidation/python/relval_steps.py +++ b/Configuration/PyReleaseValidation/python/relval_steps.py @@ -299,6 +299,7 @@ def gen2015(fragment,howMuch): steps['SingleMuPt10_UP15']=gen2015('SingleMuPt10_pythia8_cfi',Kby(25,500)) steps['SingleMuPt100_UP15']=gen2015('SingleMuPt100_pythia8_cfi',Kby(9,500)) steps['SingleMuPt1000_UP15']=gen2015('SingleMuPt1000_pythia8_cfi',Kby(9,500)) +steps['NuGun_UP15']=gen2015('SingleNuE10_cfi.py',Kby(9,100)) steps['TTbar']=gen('TTbar_8TeV_TuneCUETP8M1_cfi',Kby(9,100)) steps['TTbarLepton']=gen('TTbarLepton_8TeV_TuneCUETP8M1_cfi',Kby(9,100)) steps['ZEE']=gen('ZEE_8TeV_TuneCUETP8M1_cfi',Kby(9,100)) @@ -642,6 +643,7 @@ def addForAll(steps,d): #step1FastUpg2015Defaults steps['TTbarFS_13']=merge([{'cfg':'TTbar_13TeV_TuneCUETP8M1_cfi'},Kby(100,1000),step1FastUpg2015Defaults]) +steps['NuGunFS_UP15']=merge([{'cfg':'SingleNuE10_cfi'},Kby(100,1000),step1FastUpg2015Defaults]) steps['ZEEFS_13']=merge([{'cfg':'ZEE_13TeV_TuneCUETP8M1_cfi'},Kby(100,2000),step1FastUpg2015Defaults]) steps['ZTTFS_13']=merge([{'cfg':'ZTT_All_hadronic_13TeV_TuneCUETP8M1_cfi'},Kby(100,2000),step1FastUpg2015Defaults]) steps['ZMMFS_13']=merge([{'cfg':'ZMM_13TeV_TuneCUETP8M1_cfi'},Kby(100,2000),step1FastUpg2015Defaults]) @@ -771,14 +773,18 @@ def genvalid(fragment,d,suffix='all',fi='',dataSet=''): PUFS={'--pileup':'GEN_2012_Summer_50ns_PoissonOOTPU'} PUFS2={'--pileup':'2012_Startup_50ns_PoissonOOTPU'} PUFSAVE10={'--pileup':'GEN_AVE_10_BX_25ns'} +PUFSAVE10_DIGIRECOMIX_ITO={'--pileup':'AVE_10_BX_25ns',"--pileup_input":"file:REPLACEME_13TeV.root","--customise":"FastSimulation/Configuration/Customs.disableOOTPU"} PUFSAVE20={'--pileup':'GEN_AVE_20_BX_25ns'} +PUFS25={'--pileup':'AVE_35_BX_25ns',"--pileup_input":"file:REPLACEME_13TeV.root"} # steps['TTbarFSPU']=merge([PUFS,Kby(100,500),steps['TTbarFS']] ) -steps['TTbarFSPU2']=merge([PUFS2,Kby(100,500),steps['TTbarFS']]) -steps['TTbarFSPU13AVE10']=merge([PUFSAVE10,Kby(100,500),steps['TTbarFS_13']] ) -steps['TTbarFSPU13AVE20']=merge([PUFSAVE20,Kby(100,500),steps['TTbarFS_13']] ) +steps['FS_TTbar_13_PUAVE10']=merge([PUFSAVE10,Kby(100,500),steps['TTbarFS_13']] ) +steps['FS_TTbar_13_PUAVE20']=merge([PUFSAVE20,Kby(100,500),steps['TTbarFS_13']] ) +steps['FS_TTbar_13_PU25']=merge([PUFS25,Kby(100,500),steps['TTbarFS_13']] ) +steps['FS_NuGun_UP15_PU25']=merge([PUFS25,Kby(100,500),steps['NuGunFS_UP15']] ) +steps['FS_TTbar_13_PUAVE10_DIGIRECOMIX_ITO']=merge([PUFSAVE10_DIGIRECOMIX_ITO,Kby(100,500),steps['TTbarFS_13']] ) # step2 step2Defaults = { '-s' : 'DIGI:pdigi_valid,L1,DIGI2RAW,HLT:@fake,RAW2DIGI,L1Reco', From dae36acda38d3cb69fb4a088b8f755db6d629aa5 Mon Sep 17 00:00:00 2001 From: Lukas Date: Tue, 3 Feb 2015 20:51:52 +0100 Subject: [PATCH 2/6] forgot to add a file --- .../Configuration/python/Customs.py | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 FastSimulation/Configuration/python/Customs.py diff --git a/FastSimulation/Configuration/python/Customs.py b/FastSimulation/Configuration/python/Customs.py new file mode 100644 index 0000000000000..977a6a6c140c1 --- /dev/null +++ b/FastSimulation/Configuration/python/Customs.py @@ -0,0 +1,19 @@ +##################################### +# a bunch of handy customisation functions +# main functions: prepareGenMixing and prepareDigiRecoMixing +# author: Lukas Vanelderen +# date: Jan 21 2015 +##################################### + +import FWCore.ParameterSet.Config as cms + +def disableOOTPU(process): + process.mix.maxBunch = cms.int32(0) + process.mix.minBunch = cms.int32(0) + # set the bunch spacing + # bunch spacing matters for calorimeter calibration + # by convention bunchspace is set to 450 in case of no oot pu + process.mix.bunchspace = 450 + return process + +# more to come From e8d8cd3a6d4a73c17063cb53b298e13e5bac380b Mon Sep 17 00:00:00 2001 From: Lukas Date: Wed, 4 Feb 2015 19:53:44 +0100 Subject: [PATCH 3/6] small fix: accidentially disabled postLS1Customs for one of the new fastsim wfs --- Configuration/PyReleaseValidation/python/relval_steps.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Configuration/PyReleaseValidation/python/relval_steps.py b/Configuration/PyReleaseValidation/python/relval_steps.py index 0228c63755ddd..9e6d6175e0e4e 100644 --- a/Configuration/PyReleaseValidation/python/relval_steps.py +++ b/Configuration/PyReleaseValidation/python/relval_steps.py @@ -769,13 +769,15 @@ def genvalid(fragment,d,suffix='all',fi='',dataSet=''): PU50={'-n':10,'--pileup':'AVE_35_BX_50ns','--pileup_input':'das:/RelValMinBias_13/%s/GEN-SIM'%(baseDataSetRelease[4],)} + #PU for FastSim +FS_PU_INPUT_13TEV = "file:/afs/cern.ch/work/l/lveldere/minbias.root" PUFS={'--pileup':'GEN_2012_Summer_50ns_PoissonOOTPU'} PUFS2={'--pileup':'2012_Startup_50ns_PoissonOOTPU'} PUFSAVE10={'--pileup':'GEN_AVE_10_BX_25ns'} -PUFSAVE10_DIGIRECOMIX_ITO={'--pileup':'AVE_10_BX_25ns',"--pileup_input":"file:REPLACEME_13TeV.root","--customise":"FastSimulation/Configuration/Customs.disableOOTPU"} +PUFSAVE10_DIGIRECOMIX_ITO={'--pileup':'AVE_10_BX_25ns',"--pileup_input":FS_PU_INPUT_13TEV,"--customise":"FastSimulation/Configuration/Customs.disableOOTPU,SLHCUpgradeSimulations/Configuration/postLS1Customs.customisePostLS1"} PUFSAVE20={'--pileup':'GEN_AVE_20_BX_25ns'} -PUFS25={'--pileup':'AVE_35_BX_25ns',"--pileup_input":"file:REPLACEME_13TeV.root"} +PUFS25={'--pileup':'AVE_35_BX_25ns',"--pileup_input":FS_PU_INPUT_13TEV} # steps['TTbarFSPU']=merge([PUFS,Kby(100,500),steps['TTbarFS']] ) From 74ecee32b6bc9130a2c7fa581c4d567f34417c61 Mon Sep 17 00:00:00 2001 From: Lukas Date: Wed, 11 Feb 2015 20:38:11 +0100 Subject: [PATCH 4/6] adding another few worfklows --- Configuration/PyReleaseValidation/python/relval_pileup.py | 3 +++ Configuration/PyReleaseValidation/python/relval_steps.py | 6 +++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/Configuration/PyReleaseValidation/python/relval_pileup.py b/Configuration/PyReleaseValidation/python/relval_pileup.py index d937c63c8f80a..2dcef9b779fcf 100644 --- a/Configuration/PyReleaseValidation/python/relval_pileup.py +++ b/Configuration/PyReleaseValidation/python/relval_pileup.py @@ -36,6 +36,7 @@ workflows[50204]=['',['QQH1352T_13','DIGIUP15_PU50','RECOUP15_PU50','HARVESTUP15','MINIAODMCUP1550']] workflows[50205]=['',['ZTT_13','DIGIUP15_PU50','RECOUP15_PU50','HARVESTUP15','MINIAODMCUP1550']] workflows[50206]=['',['ZMM_13','DIGIUP15_PU50','RECOUP15_PU50','HARVESTUP15','MINIAODMCUP1550']] +workflows[50207]=['',['NuGun_UP15','DIGIUP15_PU50','RECOUP15_PU50','HARVESTUP15','MINIAODMCUP15']] # 25 ns at 13 TeV and POSTLS1 workflows[25200]=['',['ZEE_13','DIGIUP15_PU25','RECOUP15_PU25','HARVESTUP15','MINIAODMCUP15']] @@ -50,6 +51,8 @@ #fastsim workflows[25400]=['',['FS_TTbar_13_PUAVE10','HARVESTUP15FS','MINIAODMCUP15FS']] workflows[25400.1]=['',['FS_TTbar_13_PUAVE10_DIGIRECOMIX_ITO','HARVESTUP15FS','MINIAODMCUP15FS']] +workflows[25400.2]=['',['FS_TTbar_13_PUAVE35','HARVESTUP15FS','MINIAODMCUP15FS']] +workflows[25400.3]=['',['FS_TTbar_13_PUAVE35_DIGIRECOMIX_ITO','HARVESTUP15FS','MINIAODMCUP15FS']] workflows[25401]=['',['FS_TTbar_13_PUAVE20','HARVESTUP15FS','MINIAODMCUP15FS']] workflows[25402]=['',['FS_TTbar_13_PU25','HARVESTUP15FS','MINIAODMCUP15FS']] workflows[25407]=['',['FS_NuGun_UP15_PU25','HARVESTUP15FS','MINIAODMCUP15FS']] diff --git a/Configuration/PyReleaseValidation/python/relval_steps.py b/Configuration/PyReleaseValidation/python/relval_steps.py index 9e6d6175e0e4e..f7c6096bf7735 100644 --- a/Configuration/PyReleaseValidation/python/relval_steps.py +++ b/Configuration/PyReleaseValidation/python/relval_steps.py @@ -775,8 +775,10 @@ def genvalid(fragment,d,suffix='all',fi='',dataSet=''): PUFS={'--pileup':'GEN_2012_Summer_50ns_PoissonOOTPU'} PUFS2={'--pileup':'2012_Startup_50ns_PoissonOOTPU'} PUFSAVE10={'--pileup':'GEN_AVE_10_BX_25ns'} -PUFSAVE10_DIGIRECOMIX_ITO={'--pileup':'AVE_10_BX_25ns',"--pileup_input":FS_PU_INPUT_13TEV,"--customise":"FastSimulation/Configuration/Customs.disableOOTPU,SLHCUpgradeSimulations/Configuration/postLS1Customs.customisePostLS1"} PUFSAVE20={'--pileup':'GEN_AVE_20_BX_25ns'} +PUFSAVE35={'--pileup':'GEN_AVE_35_BX_25ns'} +PUFSAVE10_DIGIRECOMIX_ITO={'--pileup':'AVE_10_BX_25ns',"--pileup_input":FS_PU_INPUT_13TEV,"--customise":"FastSimulation/Configuration/Customs.disableOOTPU,SLHCUpgradeSimulations/Configuration/postLS1Customs.customisePostLS1"} +PUFSAVE35_DIGIRECOMIX_ITO={'--pileup':'AVE_35_BX_25ns',"--pileup_input":FS_PU_INPUT_13TEV,"--customise":"FastSimulation/Configuration/Customs.disableOOTPU,SLHCUpgradeSimulations/Configuration/postLS1Customs.customisePostLS1"} PUFS25={'--pileup':'AVE_35_BX_25ns',"--pileup_input":FS_PU_INPUT_13TEV} # @@ -784,9 +786,11 @@ def genvalid(fragment,d,suffix='all',fi='',dataSet=''): steps['FS_TTbar_13_PUAVE10']=merge([PUFSAVE10,Kby(100,500),steps['TTbarFS_13']] ) steps['FS_TTbar_13_PUAVE20']=merge([PUFSAVE20,Kby(100,500),steps['TTbarFS_13']] ) +steps['FS_TTbar_13_PUAVE35']=merge([PUFSAVE35,Kby(100,500),steps['TTbarFS_13']] ) steps['FS_TTbar_13_PU25']=merge([PUFS25,Kby(100,500),steps['TTbarFS_13']] ) steps['FS_NuGun_UP15_PU25']=merge([PUFS25,Kby(100,500),steps['NuGunFS_UP15']] ) steps['FS_TTbar_13_PUAVE10_DIGIRECOMIX_ITO']=merge([PUFSAVE10_DIGIRECOMIX_ITO,Kby(100,500),steps['TTbarFS_13']] ) +steps['FS_TTbar_13_PUAVE35_DIGIRECOMIX_ITO']=merge([PUFSAVE35_DIGIRECOMIX_ITO,Kby(100,500),steps['TTbarFS_13']] ) # step2 step2Defaults = { '-s' : 'DIGI:pdigi_valid,L1,DIGI2RAW,HLT:@fake,RAW2DIGI,L1Reco', From 39388b56c4f8721ea3ae9e8b731e1bfd09b09f01 Mon Sep 17 00:00:00 2001 From: Giovanni Franzoni Date: Fri, 13 Feb 2015 01:03:00 +0100 Subject: [PATCH 5/6] NuGun_UP15: ready to go for FULL-SIM --- Configuration/PyReleaseValidation/python/relval_pileup.py | 2 +- Configuration/PyReleaseValidation/python/relval_standard.py | 1 + Configuration/PyReleaseValidation/python/relval_steps.py | 3 ++- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Configuration/PyReleaseValidation/python/relval_pileup.py b/Configuration/PyReleaseValidation/python/relval_pileup.py index 2dcef9b779fcf..7c1929bd748a2 100644 --- a/Configuration/PyReleaseValidation/python/relval_pileup.py +++ b/Configuration/PyReleaseValidation/python/relval_pileup.py @@ -36,7 +36,7 @@ workflows[50204]=['',['QQH1352T_13','DIGIUP15_PU50','RECOUP15_PU50','HARVESTUP15','MINIAODMCUP1550']] workflows[50205]=['',['ZTT_13','DIGIUP15_PU50','RECOUP15_PU50','HARVESTUP15','MINIAODMCUP1550']] workflows[50206]=['',['ZMM_13','DIGIUP15_PU50','RECOUP15_PU50','HARVESTUP15','MINIAODMCUP1550']] -workflows[50207]=['',['NuGun_UP15','DIGIUP15_PU50','RECOUP15_PU50','HARVESTUP15','MINIAODMCUP15']] +workflows[50207]=['',['NuGun_UP15','DIGIUP15_PU50','RECOUP15_PU50','HARVESTUP15','MINIAODMCUP1550']] # 25 ns at 13 TeV and POSTLS1 workflows[25200]=['',['ZEE_13','DIGIUP15_PU25','RECOUP15_PU25','HARVESTUP15','MINIAODMCUP15']] diff --git a/Configuration/PyReleaseValidation/python/relval_standard.py b/Configuration/PyReleaseValidation/python/relval_standard.py index 9f7daf713c48c..52a5dd3f66578 100644 --- a/Configuration/PyReleaseValidation/python/relval_standard.py +++ b/Configuration/PyReleaseValidation/python/relval_standard.py @@ -149,6 +149,7 @@ workflows[1320] = ['', ['SingleMuPt10_UP15','DIGIUP15','RECOUP15','HARVESTUP15','MINIAODMCUP15']] workflows[1321] = ['', ['SingleMuPt100_UP15','DIGIUP15','RECOUP15','HARVESTUP15','MINIAODMCUP15']] workflows[1322] = ['', ['SingleMuPt1000_UP15','DIGIUP15','RECOUP15','HARVESTUP15','MINIAODMCUP15']] +workflows[1323] = ['', ['NuGun_UP15','DIGIUP15','RECOUP15','HARVESTUP15','MINIAODMCUP15']] ## 8 TeV workflows[24] = ['', ['TTbarLepton','DIGI','RECO','HARVEST']] diff --git a/Configuration/PyReleaseValidation/python/relval_steps.py b/Configuration/PyReleaseValidation/python/relval_steps.py index 79248148ac5dd..ba162aaabe257 100644 --- a/Configuration/PyReleaseValidation/python/relval_steps.py +++ b/Configuration/PyReleaseValidation/python/relval_steps.py @@ -432,6 +432,7 @@ def identitySim(wf): steps['SingleMuPt10_UP15INPUT']={'INPUT':InputInfo(dataSet='/RelValSingleMuPt10_UP15/%s/GEN-SIM'%(baseDataSetRelease[3],),location='STD')} steps['SingleMuPt100_UP15INPUT']={'INPUT':InputInfo(dataSet='/RelValSingleMuPt100_UP15/%s/GEN-SIM'%(baseDataSetRelease[3],),location='STD')} steps['SingleMuPt1000_UP15INPUT']={'INPUT':InputInfo(dataSet='/RelValSingleMuPt1000_UP15/%s/GEN-SIM'%(baseDataSetRelease[3],),location='STD')} +steps['NuGun_UP15INPUT']={'INPUT':InputInfo(dataSet='/RelValNuGun_UP15/%s/GEN-SIM'%(baseDataSetRelease[3],),location='STD')} #input for fast sim workflows to be added - TODO @@ -768,7 +769,7 @@ def genvalid(fragment,d,suffix='all',fi='',dataSet=''): FS_PU_INPUT_13TEV = "file:/afs/cern.ch/work/l/lveldere/minbias.root" PUFS={'--pileup':'GEN_2012_Summer_50ns_PoissonOOTPU'} PUFS2={'--pileup':'2012_Startup_50ns_PoissonOOTPU'} -PUFSAVE10={'--pileup':'GEN_AVE_10_BX_25ns'} +PUFSAVE10={'--pileup':'GEN_AVE_10_BX_25ns'} PUFSAVE20={'--pileup':'GEN_AVE_20_BX_25ns'} PUFSAVE35={'--pileup':'GEN_AVE_35_BX_25ns'} PUFSAVE10_DIGIRECOMIX_ITO={'--pileup':'AVE_10_BX_25ns',"--pileup_input":FS_PU_INPUT_13TEV,"--customise":"FastSimulation/Configuration/Customs.disableOOTPU,SLHCUpgradeSimulations/Configuration/postLS1Customs.customisePostLS1"} From ea9d3f33bb00c48609bf5687f87d7749497ec26f Mon Sep 17 00:00:00 2001 From: Giovanni Franzoni Date: Fri, 13 Feb 2015 01:23:07 +0100 Subject: [PATCH 6/6] comment out what depends on relVal we don't have before pre7 --- .../python/relval_pileup.py | 8 +++--- .../python/relval_steps.py | 28 ++++++++++--------- 2 files changed, 19 insertions(+), 17 deletions(-) diff --git a/Configuration/PyReleaseValidation/python/relval_pileup.py b/Configuration/PyReleaseValidation/python/relval_pileup.py index 7c1929bd748a2..782971776a8af 100644 --- a/Configuration/PyReleaseValidation/python/relval_pileup.py +++ b/Configuration/PyReleaseValidation/python/relval_pileup.py @@ -50,9 +50,9 @@ #fastsim workflows[25400]=['',['FS_TTbar_13_PUAVE10','HARVESTUP15FS','MINIAODMCUP15FS']] -workflows[25400.1]=['',['FS_TTbar_13_PUAVE10_DIGIRECOMIX_ITO','HARVESTUP15FS','MINIAODMCUP15FS']] +#workflows[25400.1]=['',['FS_TTbar_13_PUAVE10_DIGIRECOMIX_ITO','HARVESTUP15FS','MINIAODMCUP15FS']] workflows[25400.2]=['',['FS_TTbar_13_PUAVE35','HARVESTUP15FS','MINIAODMCUP15FS']] -workflows[25400.3]=['',['FS_TTbar_13_PUAVE35_DIGIRECOMIX_ITO','HARVESTUP15FS','MINIAODMCUP15FS']] +#workflows[25400.3]=['',['FS_TTbar_13_PUAVE35_DIGIRECOMIX_ITO','HARVESTUP15FS','MINIAODMCUP15FS']] workflows[25401]=['',['FS_TTbar_13_PUAVE20','HARVESTUP15FS','MINIAODMCUP15FS']] -workflows[25402]=['',['FS_TTbar_13_PU25','HARVESTUP15FS','MINIAODMCUP15FS']] -workflows[25407]=['',['FS_NuGun_UP15_PU25','HARVESTUP15FS','MINIAODMCUP15FS']] +#workflows[25402]=['',['FS_TTbar_13_PU25','HARVESTUP15FS','MINIAODMCUP15FS']] +#workflows[25407]=['',['FS_NuGun_UP15_PU25','HARVESTUP15FS','MINIAODMCUP15FS']] diff --git a/Configuration/PyReleaseValidation/python/relval_steps.py b/Configuration/PyReleaseValidation/python/relval_steps.py index ba162aaabe257..6551ae5c732f5 100644 --- a/Configuration/PyReleaseValidation/python/relval_steps.py +++ b/Configuration/PyReleaseValidation/python/relval_steps.py @@ -766,26 +766,28 @@ def genvalid(fragment,d,suffix='all',fi='',dataSet=''): #PU for FastSim -FS_PU_INPUT_13TEV = "file:/afs/cern.ch/work/l/lveldere/minbias.root" +# FS_PU_INPUT_13TEV = "file:/afs/cern.ch/work/l/lveldere/minbias.root" # placeholder for relval to be produced with wf 135.8 PUFS={'--pileup':'GEN_2012_Summer_50ns_PoissonOOTPU'} -PUFS2={'--pileup':'2012_Startup_50ns_PoissonOOTPU'} -PUFSAVE10={'--pileup':'GEN_AVE_10_BX_25ns'} -PUFSAVE20={'--pileup':'GEN_AVE_20_BX_25ns'} +# PUFS2={'--pileup':'2012_Startup_50ns_PoissonOOTPU'} # not used anywhere +PUFSAVE10={'--pileup':'GEN_AVE_10_BX_25ns'} # temporary: one or a few releases as back-up +PUFSAVE20={'--pileup':'GEN_AVE_20_BX_25ns'} # temporary: one or a few releases as back-up PUFSAVE35={'--pileup':'GEN_AVE_35_BX_25ns'} -PUFSAVE10_DIGIRECOMIX_ITO={'--pileup':'AVE_10_BX_25ns',"--pileup_input":FS_PU_INPUT_13TEV,"--customise":"FastSimulation/Configuration/Customs.disableOOTPU,SLHCUpgradeSimulations/Configuration/postLS1Customs.customisePostLS1"} -PUFSAVE35_DIGIRECOMIX_ITO={'--pileup':'AVE_35_BX_25ns',"--pileup_input":FS_PU_INPUT_13TEV,"--customise":"FastSimulation/Configuration/Customs.disableOOTPU,SLHCUpgradeSimulations/Configuration/postLS1Customs.customisePostLS1"} -PUFS25={'--pileup':'AVE_35_BX_25ns',"--pileup_input":FS_PU_INPUT_13TEV} +# PUFSAVE10_DIGIRECOMIX_ITO={'--pileup':'AVE_10_BX_25ns',"--pileup_input":FS_PU_INPUT_13TEV,"--customise":"FastSimulation/Configuration/Customs.disableOOTPU,SLHCUpgradeSimulations/Configuration/postLS1Customs.customisePostLS1"} +# temporary: one or a few releases as back-up; needs the placeholder +#PUFSAVE35_DIGIRECOMIX_ITO={'--pileup':'AVE_35_BX_25ns',"--pileup_input":FS_PU_INPUT_13TEV,"--customise":"FastSimulation/Configuration/Customs.disableOOTPU,SLHCUpgradeSimulations/Configuration/postLS1Customs.customisePostLS1"} +# temporary: one or a few releases as back-up; needs the placeholder +# PUFS25={'--pileup':'AVE_35_BX_25ns',"--pileup_input":FS_PU_INPUT_13TEV} # needs the placeholder # steps['TTbarFSPU']=merge([PUFS,Kby(100,500),steps['TTbarFS']] ) -steps['FS_TTbar_13_PUAVE10']=merge([PUFSAVE10,Kby(100,500),steps['TTbarFS_13']] ) -steps['FS_TTbar_13_PUAVE20']=merge([PUFSAVE20,Kby(100,500),steps['TTbarFS_13']] ) +steps['FS_TTbar_13_PUAVE10']=merge([PUFSAVE10,Kby(100,500),steps['TTbarFS_13']] ) # temporary: one or a few releases as back-up +steps['FS_TTbar_13_PUAVE20']=merge([PUFSAVE20,Kby(100,500),steps['TTbarFS_13']] ) # temporary: one or a few releases as back-up steps['FS_TTbar_13_PUAVE35']=merge([PUFSAVE35,Kby(100,500),steps['TTbarFS_13']] ) -steps['FS_TTbar_13_PU25']=merge([PUFS25,Kby(100,500),steps['TTbarFS_13']] ) -steps['FS_NuGun_UP15_PU25']=merge([PUFS25,Kby(100,500),steps['NuGunFS_UP15']] ) -steps['FS_TTbar_13_PUAVE10_DIGIRECOMIX_ITO']=merge([PUFSAVE10_DIGIRECOMIX_ITO,Kby(100,500),steps['TTbarFS_13']] ) -steps['FS_TTbar_13_PUAVE35_DIGIRECOMIX_ITO']=merge([PUFSAVE35_DIGIRECOMIX_ITO,Kby(100,500),steps['TTbarFS_13']] ) +# steps['FS_TTbar_13_PU25']=merge([PUFS25,Kby(100,500),steps['TTbarFS_13']] ) # needs the placeholder +# steps['FS_NuGun_UP15_PU25']=merge([PUFS25,Kby(100,500),steps['NuGunFS_UP15']] ) # needs the placeholder +#steps['FS_TTbar_13_PUAVE10_DIGIRECOMIX_ITO']=merge([PUFSAVE10_DIGIRECOMIX_ITO,Kby(100,500),steps['TTbarFS_13']] ) # needs the placeholder +#steps['FS_TTbar_13_PUAVE35_DIGIRECOMIX_ITO']=merge([PUFSAVE35_DIGIRECOMIX_ITO,Kby(100,500),steps['TTbarFS_13']] ) # needs the placeholder # step2 step2Defaults = { '-s' : 'DIGI:pdigi_valid,L1,DIGI2RAW,HLT:@fake,RAW2DIGI,L1Reco',