diff --git a/data/Espressif-Community/README.md b/data/Espressif-Community/README.md index a5f93650..817b7ec8 100644 --- a/data/Espressif-Community/README.md +++ b/data/Espressif-Community/README.md @@ -7,3 +7,5 @@ could not be extracted automatically. * esp32.svd: copied from the file at https://github.com/esp-rs/esp32/blob/master/svd/esp32.svd + * esp8266.svd: generated using `make` from the repo: + https://github.com/esp-rs/esp8266 diff --git a/data/Espressif-Community/esp8266.svd b/data/Espressif-Community/esp8266.svd new file mode 100644 index 00000000..d24a7b31 --- /dev/null +++ b/data/Espressif-Community/esp8266.svd @@ -0,0 +1,6953 @@ + + esp8266 + 1.0 + 32 + + Xtensa LX106 + 1 + little + false + true + 3 + false + + + + DPORT + 0x3ff00000 + + 0 + 0x00000040 + registers + + + + EDGE_INT_ENABLE + 0x4 + EDGE_INT_ENABLE + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + wdt_edge_int_enableEnable the watchdog timer edge interrupt01 + timer1_edge_int_enableEnable the timer1 edge interrupt11 + + + + DPORT_CTL + 0x14 + DPORT_CTL + 32 + 0x00000000 + + + DPORT_CTL_DOUBLE_CLK + 0 + 1 + read-write + + + + + + + EFUSE + 0x3ff00050 + + 0 + 0x00000080 + registers + + + + EFUSE_DATA0 + 0x0 + EFUSE_DATA0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + EFUSE_DATA1 + 0x4 + EFUSE_DATA1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + EFUSE_DATA2 + 0x8 + EFUSE_DATA2 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + EFUSE_DATA3 + 0xc + EFUSE_DATA3 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + + + GPIO + 0x60000300 + + 0 + 0x000003a0 + registers + + + + GPIO_OUT + 0x0 + BT-Coexist Selection register + 32 + 0x00000000 + + + GPIO_BT_SEL + BT-Coexist Selection register + 16 + 16 + read-write + + + GPIO_OUT_DATA + The output value when the GPIO pin is set as output. + 0 + 16 + read-write + + + + + GPIO_OUT_W1TS + 0x4 + GPIO_OUT_W1TS + 32 + 0x00000000 + + + GPIO_OUT_DATA_W1TS + Writing 1 into a bit in this register will set the related bit in + GPIO_OUT_DATA + + 0 + 16 + write-only + + + + + GPIO_OUT_W1TC + 0x8 + GPIO_OUT_W1TC + 32 + 0x00000000 + + + GPIO_OUT_DATA_W1TC + Writing 1 into a bit in this register will clear the related bit in + GPIO_OUT_DATA + + 0 + 16 + write-only + + + + + GPIO_ENABLE + 0xc + GPIO_ENABLE + 32 + 0x00000000 + + + GPIO_SDIO_SEL + SDIO-dis selection register + 16 + 6 + read-write + + + GPIO_ENABLE_DATA + The output enable register. + 0 + 16 + read-write + + + + + GPIO_ENABLE_W1TS + 0x10 + GPIO_ENABLE_W1TS + 32 + 0x00000000 + + + GPIO_ENABLE_DATA_W1TS + Writing 1 into a bit in this register will set the related bit in + GPIO_ENABLE_DATA + + 0 + 16 + write-only + + + + + GPIO_ENABLE_W1TC + 0x14 + GPIO_ENABLE_W1TC + 32 + 0x00000000 + + + GPIO_ENABLE_DATA_W1TC + Writing 1 into a bit in this register will clear the related bit in + GPIO_ENABLE_DATA + + 0 + 16 + write-only + + + + + GPIO_IN + 0x18 + The values of the strapping pins. + 32 + 0x00000000 + + + GPIO_STRAPPING + The values of the strapping pins. + 16 + 16 + read-write + + + GPIO_IN_DATA + The values of the GPIO pins when the GPIO pin is set as input. + 0 + 16 + read-write + + + + + GPIO_STATUS + 0x1c + GPIO_STATUS + 32 + 0x00000000 + + + GPIO_STATUS_INTERRUPT + Interrupt enable register. + 0 + 16 + read-write + + + + + GPIO_STATUS_W1TS + 0x20 + GPIO_STATUS_W1TS + 32 + 0x00000000 + + + GPIO_STATUS_INTERRUPT_W1TS + Writing 1 into a bit in this register will set the related bit in + GPIO_STATUS_INTERRUPT + + 0 + 16 + write-only + + + + + GPIO_STATUS_W1TC + 0x24 + GPIO_STATUS_W1TC + 32 + 0x00000000 + + + GPIO_STATUS_INTERRUPT_W1TC + Writing 1 into a bit in this register will clear the related bit in + GPIO_STATUS_INTERRUPT + + 0 + 16 + write-only + + + + + GPIO_PIN0 + 0x28 + GPIO_PIN0 + 32 + 0x00000000 + + + GPIO_PIN0_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN0_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN0_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN0_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN0_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN0_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN0_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN1 + 0x2c + GPIO_PIN1 + 32 + 0x00000000 + + + GPIO_PIN1_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN1_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN1_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN1_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN1_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN1_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN1_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN2 + 0x30 + GPIO_PIN2 + 32 + 0x00000000 + + + GPIO_PIN2_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN2_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN2_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN2_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN2_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN2_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN2_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN3 + 0x34 + GPIO_PIN3 + 32 + 0x00000000 + + + GPIO_PIN3_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN3_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN3_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN3_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN3_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN3_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN3_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN4 + 0x38 + GPIO_PIN4 + 32 + 0x00000000 + + + GPIO_PIN4_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN4_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN4_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN4_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN4_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN4_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN4_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN5 + 0x3c + GPIO_PIN5 + 32 + 0x00000000 + + + GPIO_PIN5_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN5_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN5_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN5_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN5_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN5_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN5_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN6 + 0x40 + GPIO_PIN6 + 32 + 0x00000000 + + + GPIO_PIN6_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN6_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN6_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN6_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN6_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN6_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN6_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN7 + 0x44 + GPIO_PIN7 + 32 + 0x00000000 + + + GPIO_PIN7_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN7_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN7_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN7_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN7_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN7_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN7_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN8 + 0x48 + GPIO_PIN8 + 32 + 0x00000000 + + + GPIO_PIN8_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN8_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN8_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN8_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN8_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN8_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN8_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN9 + 0x4c + GPIO_PIN9 + 32 + 0x00000000 + + + GPIO_PIN9_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN9_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN9_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN9_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN9_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN9_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN9_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN10 + 0x50 + GPIO_PIN10 + 32 + 0x00000000 + + + GPIO_PIN10_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN10_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN10_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN10_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN10_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN10_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN10_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN11 + 0x54 + GPIO_PIN11 + 32 + 0x00000000 + + + GPIO_PIN11_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN11_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN11_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN11_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN11_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN11_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN11_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN12 + 0x58 + GPIO_PIN12 + 32 + 0x00000000 + + + GPIO_PIN12_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN12_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN12_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN12_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN12_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN12_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN12_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN13 + 0x5c + GPIO_PIN13 + 32 + 0x00000000 + + + GPIO_PIN13_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN13_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN13_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN13_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN13_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN13_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN13_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN14 + 0x60 + GPIO_PIN14 + 32 + 0x00000000 + + + GPIO_PIN14_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN14_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN14_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN14_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN14_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN14_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN14_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_PIN15 + 0x64 + GPIO_PIN15 + 32 + 0x00000000 + + + GPIO_PIN15_WAKEUP_ENABLE + 0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or + 0x5 + + 10 + 1 + read-write + + + GPIO_PIN15_INT_TYPE + 0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: + low-level; 5: high-level + + 7 + 3 + read-write + GPIO_PIN15_INT_TYPEread-writedisabledinterrupt is disabled0positive_edgeinterrupt is triggered on the positive edge1negative_edgeinterrupt is triggered on the negative edge2both_edgesinterrupt is triggered on both edges3low_levelinterrupt is triggered on the low level4high_levelinterrupt is triggered on the high level5 + + + GPIO_PIN15_DRIVER + 1: open drain; 0: normal + 2 + 1 + read-write + GPIO_PIN15_DRIVERread-writeopen_drainopen drain0normalnormal1 + + + GPIO_PIN15_SOURCE + 1: sigma-delta; 0: GPIO_DATA + 0 + 1 + read-write + GPIO_PIN15_SOURCEread-writesigma_deltasigma-delta0gpio_datagpio data1 + + + + + GPIO_SIGMA_DELTA + 0x68 + GPIO_SIGMA_DELTA + 32 + 0x00000000 + + + SIGMA_DELTA_ENABLE + 1: enable sigma-delta; 0: disable + 16 + 1 + read-write + + + SIGMA_DELTA_PRESCALAR + Clock pre-divider for sigma-delta. + 8 + 8 + read-write + + + SIGMA_DELTA_TARGET + target level of the sigma-delta. It is a signed byte. + 0 + 8 + read-write + + + + + GPIO_RTC_CALIB_SYNC + 0x6c + Positvie edge of this bit will trigger the RTC-clock-calibration process. + 32 + 0x00000000 + + + RTC_CALIB_START + Positvie edge of this bit will trigger the RTC-clock-calibration process. + + 31 + 1 + read-write + + + RTC_PERIOD_NUM + The cycle number of RTC-clock during RTC-clock-calibration + 0 + 10 + read-write + + + + + GPIO_RTC_CALIB_VALUE + 0x70 + 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done + 32 + 0x00000000 + + + RTC_CALIB_RDY + 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done + 31 + 1 + read-write + + + RTC_CALIB_RDY_REAL + 0: during RTC-clock-calibration; 1: RTC-clock-calibration is done + 30 + 1 + read-write + + + RTC_CALIB_VALUE + The cycle number of clk_xtal (crystal clock) for the RTC_PERIOD_NUM cycles of + RTC-clock + + 0 + 20 + read-write + + + + + + + I2S + 0x60000e00 + + 0 + 0x00000160 + registers + + + + I2STXFIFO + 0x0 + I2STXFIFO + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + I2SRXFIFO + 0x4 + I2SRXFIFO + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + I2SCONF + 0x8 + I2SCONF + 32 + 0x00000000 + + + I2S_BCK_DIV_NUM + 22 + 6 + read-write + + + I2S_CLKM_DIV_NUM + 16 + 6 + read-write + + + I2S_BITS_MOD + 12 + 4 + read-write + + + I2S_RECE_MSB_SHIFT + 11 + 1 + read-write + + + I2S_TRANS_MSB_SHIFT + 10 + 1 + read-write + + + I2S_I2S_RX_START + 9 + 1 + read-write + + + I2S_I2S_TX_START + 8 + 1 + read-write + + + I2S_MSB_RIGHT + 7 + 1 + read-write + + + I2S_RIGHT_FIRST + 6 + 1 + read-write + + + I2S_RECE_SLAVE_MOD + 5 + 1 + read-write + + + I2S_TRANS_SLAVE_MOD + 4 + 1 + read-write + + + I2S_I2S_RX_FIFO_RESET + 3 + 1 + read-write + + + I2S_I2S_TX_FIFO_RESET + 2 + 1 + read-write + + + I2S_I2S_RX_RESET + 1 + 1 + read-write + + + I2S_I2S_TX_RESET + 0 + 1 + read-write + + + + + I2SINT_RAW + 0xc + I2SINT_RAW + 32 + 0x00000000 + + + I2S_I2S_TX_REMPTY_INT_RAW + 5 + 1 + read-write + + + I2S_I2S_TX_WFULL_INT_RAW + 4 + 1 + read-write + + + I2S_I2S_RX_REMPTY_INT_RAW + 3 + 1 + read-write + + + I2S_I2S_RX_WFULL_INT_RAW + 2 + 1 + read-write + + + I2S_I2S_TX_PUT_DATA_INT_RAW + 1 + 1 + read-write + + + I2S_I2S_RX_TAKE_DATA_INT_RAW + 0 + 1 + read-write + + + + + I2SINT_ST + 0x10 + I2SINT_ST + 32 + 0x00000000 + + + I2S_I2S_TX_REMPTY_INT_ST + 5 + 1 + read-write + + + I2S_I2S_TX_WFULL_INT_ST + 4 + 1 + read-write + + + I2S_I2S_RX_REMPTY_INT_ST + 3 + 1 + read-write + + + I2S_I2S_RX_WFULL_INT_ST + 2 + 1 + read-write + + + I2S_I2S_TX_PUT_DATA_INT_ST + 1 + 1 + read-write + + + I2S_I2S_RX_TAKE_DATA_INT_ST + 0 + 1 + read-write + + + + + I2SINT_ENA + 0x14 + I2SINT_ENA + 32 + 0x00000000 + + + I2S_I2S_TX_REMPTY_INT_ENA + 5 + 1 + read-write + + + I2S_I2S_TX_WFULL_INT_ENA + 4 + 1 + read-write + + + I2S_I2S_RX_REMPTY_INT_ENA + 3 + 1 + read-write + + + I2S_I2S_RX_WFULL_INT_ENA + 2 + 1 + read-write + + + I2S_I2S_TX_PUT_DATA_INT_ENA + 1 + 1 + read-write + + + I2S_I2S_RX_TAKE_DATA_INT_ENA + 0 + 1 + read-write + + + + + I2SINT_CLR + 0x18 + I2SINT_CLR + 32 + 0x00000000 + + + I2S_I2S_TX_REMPTY_INT_CLR + 5 + 1 + read-write + + + I2S_I2S_TX_WFULL_INT_CLR + 4 + 1 + read-write + + + I2S_I2S_RX_REMPTY_INT_CLR + 3 + 1 + read-write + + + I2S_I2S_RX_WFULL_INT_CLR + 2 + 1 + read-write + + + I2S_I2S_PUT_DATA_INT_CLR + 1 + 1 + read-write + + + I2S_I2S_TAKE_DATA_INT_CLR + 0 + 1 + read-write + + + + + I2STIMING + 0x1c + I2STIMING + 32 + 0x00000000 + + + I2S_TRANS_BCK_IN_INV + 22 + 1 + read-write + + + I2S_RECE_DSYNC_SW + 21 + 1 + read-write + + + I2S_TRANS_DSYNC_SW + 20 + 1 + read-write + + + I2S_RECE_BCK_OUT_DELAY + 18 + 2 + read-write + + + I2S_RECE_WS_OUT_DELAY + 16 + 2 + read-write + + + I2S_TRANS_SD_OUT_DELAY + 14 + 2 + read-write + + + I2S_TRANS_WS_OUT_DELAY + 12 + 2 + read-write + + + I2S_TRANS_BCK_OUT_DELAY + 10 + 2 + read-write + + + I2S_RECE_SD_IN_DELAY + 8 + 2 + read-write + + + I2S_RECE_WS_IN_DELAY + 6 + 2 + read-write + + + I2S_RECE_BCK_IN_DELAY + 4 + 2 + read-write + + + I2S_TRANS_WS_IN_DELAY + 2 + 2 + read-write + + + I2S_TRANS_BCK_IN_DELAY + 0 + 2 + read-write + + + + + I2S_FIFO_CONF + 0x20 + I2S_FIFO_CONF + 32 + 0x00000000 + + + I2S_I2S_RX_FIFO_MOD + 16 + 3 + read-write + + + I2S_I2S_TX_FIFO_MOD + 13 + 3 + read-write + + + I2S_I2S_DSCR_EN + 12 + 1 + read-write + + + I2S_I2S_TX_DATA_NUM + 6 + 6 + read-write + + + I2S_I2S_RX_DATA_NUM + 0 + 6 + read-write + + + + + I2SRXEOF_NUM + 0x24 + I2SRXEOF_NUM + 32 + 0x00000000 + + + I2S_I2S_RX_EOF_NUM + 0 + 32 + read-write + + + + + I2SCONF_SIGLE_DATA + 0x28 + I2SCONF_SIGLE_DATA + 32 + 0x00000000 + + + I2S_I2S_SIGLE_DATA + 0 + 32 + read-write + + + + + + + IO_MUX + 0x60000800 + + 0 + 0x00000220 + registers + + + + IO_MUX_CONF + 0x0 + IO_MUX_CONF + 32 + 0x00000000 + + + SPI0_CLK_EQU_SYS_CLK + 8 + 1 + read-write + + + SPI1_CLK_EQU_SYS_CLK + 9 + 1 + read-write + + + + + IO_MUX_MTDI + 0x4 + IO_MUX_MTDI + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_MTCK + 0x8 + IO_MUX_MTCK + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_MTMS + 0xc + IO_MUX_MTMS + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_MTDO + 0x10 + IO_MUX_MTDO + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_U0RXD + 0x14 + IO_MUX_U0RXD + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_U0TXD + 0x18 + IO_MUX_U0TXD + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_SD_CLK + 0x1c + IO_MUX_SD_CLK + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_SD_DATA0 + 0x20 + IO_MUX_SD_DATA0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_SD_DATA1 + 0x24 + IO_MUX_SD_DATA1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_SD_DATA2 + 0x28 + IO_MUX_SD_DATA2 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_SD_DATA3 + 0x2c + IO_MUX_SD_DATA3 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_SD_CMD + 0x30 + IO_MUX_SD_CMD + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_GPIO0 + 0x34 + IO_MUX_GPIO0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_GPIO2 + 0x38 + IO_MUX_GPIO2 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_GPIO4 + 0x3c + IO_MUX_GPIO4 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + IO_MUX_GPIO5 + 0x40 + IO_MUX_GPIO5 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + FUNCTION_SELECT_LOW_BITSconfigures IO_MUX function, bottom 2 bits42 + FUNCTION_SELECT_HIGH_BITconfigures IO_MUX function, upper bit81 + PULLUPconfigures pull up71 + SLEEP_PULLUPconfigures pull up during sleep mode31 + SLEEP_ENABLEconfigures output enable during sleep mode01 + + + + + + RTC + 0x60000700 + + 0 + 0x00000040 + registers + + + + RTC_STORE0 + 0x30 + RTC_STORE0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + RTC_STATE1 + 0x14 + RTC_STATE1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + + + SLC + 0x60000b00 + + 0 + 0x00000400 + registers + + + + SLC_CONF0 + 0x0 + SLC_CONF0 + 32 + 0x00000000 + + + SLC_MODE + 12 + 2 + read-write + + + SLC_DATA_BURST_EN + 9 + 1 + read-write + + + SLC_DSCR_BURST_EN + 8 + 1 + read-write + + + SLC_RX_NO_RESTART_CLR + 7 + 1 + read-write + + + SLC_RX_AUTO_WRBACK + 6 + 1 + read-write + + + SLC_RX_LOOP_TEST + 5 + 1 + read-write + + + SLC_TX_LOOP_TEST + 4 + 1 + read-write + + + SLC_AHBM_RST + 3 + 1 + read-write + + + SLC_AHBM_FIFO_RST + 2 + 1 + read-write + + + SLC_RXLINK_RST + 1 + 1 + read-write + + + SLC_TXLINK_RST + 0 + 1 + read-write + + + + + SLC_INT_RAW + 0x4 + SLC_INT_RAW + 32 + 0x00000000 + + + SLC_TX_DSCR_EMPTY_INT_RAW + 21 + 1 + read-write + + + SLC_RX_DSCR_ERR_INT_RAW + 20 + 1 + read-write + + + SLC_TX_DSCR_ERR_INT_RAW + 19 + 1 + read-write + + + SLC_TOHOST_INT_RAW + 18 + 1 + read-write + + + SLC_RX_EOF_INT_RAW + 17 + 1 + read-write + + + SLC_RX_DONE_INT_RAW + 16 + 1 + read-write + + + SLC_TX_EOF_INT_RAW + 15 + 1 + read-write + + + SLC_TX_DONE_INT_RAW + 14 + 1 + read-write + + + SLC_TOKEN1_1TO0_INT_RAW + 13 + 1 + read-write + + + SLC_TOKEN0_1TO0_INT_RAW + 12 + 1 + read-write + + + SLC_TX_OVF_INT_RAW + 11 + 1 + read-write + + + SLC_RX_UDF_INT_RAW + 10 + 1 + read-write + + + SLC_TX_START_INT_RAW + 9 + 1 + read-write + + + SLC_RX_START_INT_RAW + 8 + 1 + read-write + + + SLC_FRHOST_BIT7_INT_RAW + 7 + 1 + read-write + + + SLC_FRHOST_BIT6_INT_RAW + 6 + 1 + read-write + + + SLC_FRHOST_BIT5_INT_RAW + 5 + 1 + read-write + + + SLC_FRHOST_BIT4_INT_RAW + 4 + 1 + read-write + + + SLC_FRHOST_BIT3_INT_RAW + 3 + 1 + read-write + + + SLC_FRHOST_BIT2_INT_RAW + 2 + 1 + read-write + + + SLC_FRHOST_BIT1_INT_RAW + 1 + 1 + read-write + + + SLC_FRHOST_BIT0_INT_RAW + 0 + 1 + read-write + + + + + SLC_INT_STATUS + 0x8 + SLC_INT_STATUS + 32 + 0x00000000 + + + SLC_TX_DSCR_EMPTY_INT_ST + 21 + 1 + read-write + + + SLC_RX_DSCR_ERR_INT_ST + 20 + 1 + read-write + + + SLC_TX_DSCR_ERR_INT_ST + 19 + 1 + read-write + + + SLC_TOHOST_INT_ST + 18 + 1 + read-write + + + SLC_RX_EOF_INT_ST + 17 + 1 + read-write + + + SLC_RX_DONE_INT_ST + 16 + 1 + read-write + + + SLC_TX_EOF_INT_ST + 15 + 1 + read-write + + + SLC_TX_DONE_INT_ST + 14 + 1 + read-write + + + SLC_TOKEN1_1TO0_INT_ST + 13 + 1 + read-write + + + SLC_TOKEN0_1TO0_INT_ST + 12 + 1 + read-write + + + SLC_TX_OVF_INT_ST + 11 + 1 + read-write + + + SLC_RX_UDF_INT_ST + 10 + 1 + read-write + + + SLC_TX_START_INT_ST + 9 + 1 + read-write + + + SLC_RX_START_INT_ST + 8 + 1 + read-write + + + SLC_FRHOST_BIT7_INT_ST + 7 + 1 + read-write + + + SLC_FRHOST_BIT6_INT_ST + 6 + 1 + read-write + + + SLC_FRHOST_BIT5_INT_ST + 5 + 1 + read-write + + + SLC_FRHOST_BIT4_INT_ST + 4 + 1 + read-write + + + SLC_FRHOST_BIT3_INT_ST + 3 + 1 + read-write + + + SLC_FRHOST_BIT2_INT_ST + 2 + 1 + read-write + + + SLC_FRHOST_BIT1_INT_ST + 1 + 1 + read-write + + + SLC_FRHOST_BIT0_INT_ST + 0 + 1 + read-write + + + + + SLC_INT_ENA + 0xc + SLC_INT_ENA + 32 + 0x00000000 + + + SLC_TX_DSCR_EMPTY_INT_ENA + 21 + 1 + read-write + + + SLC_RX_DSCR_ERR_INT_ENA + 20 + 1 + read-write + + + SLC_TX_DSCR_ERR_INT_ENA + 19 + 1 + read-write + + + SLC_TOHOST_INT_ENA + 18 + 1 + read-write + + + SLC_RX_EOF_INT_ENA + 17 + 1 + read-write + + + SLC_RX_DONE_INT_ENA + 16 + 1 + read-write + + + SLC_TX_EOF_INT_ENA + 15 + 1 + read-write + + + SLC_TX_DONE_INT_ENA + 14 + 1 + read-write + + + SLC_TOKEN1_1TO0_INT_ENA + 13 + 1 + read-write + + + SLC_TOKEN0_1TO0_INT_ENA + 12 + 1 + read-write + + + SLC_TX_OVF_INT_ENA + 11 + 1 + read-write + + + SLC_RX_UDF_INT_ENA + 10 + 1 + read-write + + + SLC_TX_START_INT_ENA + 9 + 1 + read-write + + + SLC_RX_START_INT_ENA + 8 + 1 + read-write + + + SLC_FRHOST_BIT7_INT_ENA + 7 + 1 + read-write + + + SLC_FRHOST_BIT6_INT_ENA + 6 + 1 + read-write + + + SLC_FRHOST_BIT5_INT_ENA + 5 + 1 + read-write + + + SLC_FRHOST_BIT4_INT_ENA + 4 + 1 + read-write + + + SLC_FRHOST_BIT3_INT_ENA + 3 + 1 + read-write + + + SLC_FRHOST_BIT2_INT_ENA + 2 + 1 + read-write + + + SLC_FRHOST_BIT1_INT_ENA + 1 + 1 + read-write + + + SLC_FRHOST_BIT0_INT_ENA + 0 + 1 + read-write + + + + + SLC_INT_CLR + 0x10 + SLC_INT_CLR + 32 + 0x00000000 + + + SLC_TX_DSCR_EMPTY_INT_CLR + 21 + 1 + read-write + + + SLC_RX_DSCR_ERR_INT_CLR + 20 + 1 + read-write + + + SLC_TX_DSCR_ERR_INT_CLR + 19 + 1 + read-write + + + SLC_TOHOST_INT_CLR + 18 + 1 + read-write + + + SLC_RX_EOF_INT_CLR + 17 + 1 + read-write + + + SLC_RX_DONE_INT_CLR + 16 + 1 + read-write + + + SLC_TX_EOF_INT_CLR + 15 + 1 + read-write + + + SLC_TX_DONE_INT_CLR + 14 + 1 + read-write + + + SLC_TOKEN1_1TO0_INT_CLR + 13 + 1 + read-write + + + SLC_TOKEN0_1TO0_INT_CLR + 12 + 1 + read-write + + + SLC_TX_OVF_INT_CLR + 11 + 1 + read-write + + + SLC_RX_UDF_INT_CLR + 10 + 1 + read-write + + + SLC_TX_START_INT_CLR + 9 + 1 + read-write + + + SLC_RX_START_INT_CLR + 8 + 1 + read-write + + + SLC_FRHOST_BIT7_INT_CLR + 7 + 1 + read-write + + + SLC_FRHOST_BIT6_INT_CLR + 6 + 1 + read-write + + + SLC_FRHOST_BIT5_INT_CLR + 5 + 1 + read-write + + + SLC_FRHOST_BIT4_INT_CLR + 4 + 1 + read-write + + + SLC_FRHOST_BIT3_INT_CLR + 3 + 1 + read-write + + + SLC_FRHOST_BIT2_INT_CLR + 2 + 1 + read-write + + + SLC_FRHOST_BIT1_INT_CLR + 1 + 1 + read-write + + + SLC_FRHOST_BIT0_INT_CLR + 0 + 1 + read-write + + + + + SLC_RX_STATUS + 0x14 + SLC_RX_STATUS + 32 + 0x00000000 + + + SLC_RX_EMPTY + 1 + 1 + read-write + + + SLC_RX_FULL + 0 + 1 + read-write + + + + + SLC_RX_FIFO_PUSH + 0x18 + SLC_RX_FIFO_PUSH + 32 + 0x00000000 + + + SLC_RXFIFO_PUSH + 16 + 1 + read-write + + + SLC_RXFIFO_WDATA + 0 + 9 + read-write + + + + + SLC_TX_STATUS + 0x1c + SLC_TX_STATUS + 32 + 0x00000000 + + + SLC_TX_EMPTY + 1 + 1 + read-write + + + SLC_TX_FULL + 0 + 1 + read-write + + + + + SLC_TX_FIFO_POP + 0x20 + SLC_TX_FIFO_POP + 32 + 0x00000000 + + + SLC_TXFIFO_POP + 16 + 1 + read-write + + + SLC_TXFIFO_RDATA + 0 + 11 + read-write + + + + + SLC_RX_LINK + 0x24 + SLC_RX_LINK + 32 + 0x00000000 + + + SLC_RXLINK_PARK + 31 + 1 + read-write + + + SLC_RXLINK_RESTART + 30 + 1 + read-write + + + SLC_RXLINK_START + 29 + 1 + read-write + + + SLC_RXLINK_STOP + 28 + 1 + read-write + + + SLC_RXLINK_ADDR + 0 + 20 + read-write + + + + + SLC_TX_LINK + 0x28 + SLC_TX_LINK + 32 + 0x00000000 + + + SLC_TXLINK_PARK + 31 + 1 + read-write + + + SLC_TXLINK_RESTART + 30 + 1 + read-write + + + SLC_TXLINK_START + 29 + 1 + read-write + + + SLC_TXLINK_STOP + 28 + 1 + read-write + + + SLC_TXLINK_ADDR + 0 + 20 + read-write + + + + + SLC_INTVEC_TOHOST + 0x2c + SLC_INTVEC_TOHOST + 32 + 0x00000000 + + + SLC_TOHOST_INTVEC + 0 + 8 + read-write + + + + + SLC_TOKEN0 + 0x30 + SLC_TOKEN0 + 32 + 0x00000000 + + + SLC_TOKEN0 + 16 + 12 + read-write + + + SLC_TOKEN0_LOCAL_INC_MORE + 14 + 1 + read-write + + + SLC_TOKEN0_LOCAL_INC + 13 + 1 + read-write + + + SLC_TOKEN0_LOCAL_WR + 12 + 1 + read-write + + + SLC_TOKEN0_LOCAL_WDATA + 0 + 12 + read-write + + + + + SLC_TOKEN1 + 0x34 + SLC_TOKEN1 + 32 + 0x00000000 + + + SLC_TOKEN1 + 16 + 12 + read-write + + + SLC_TOKEN1_LOCAL_INC_MORE + 14 + 1 + read-write + + + SLC_TOKEN1_LOCAL_INC + 13 + 1 + read-write + + + SLC_TOKEN1_LOCAL_WR + 12 + 1 + read-write + + + SLC_TOKEN1_LOCAL_WDATA + 0 + 12 + read-write + + + + + SLC_CONF1 + 0x38 + SLC_CONF1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_STATE0 + 0x3c + SLC_STATE0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_STATE1 + 0x40 + SLC_STATE1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_BRIDGE_CONF + 0x44 + SLC_BRIDGE_CONF + 32 + 0x00000000 + + + SLC_TX_PUSH_IDLE_NUM + 16 + 16 + read-write + + + SLC_TX_DUMMY_MODE + 12 + 1 + read-write + + + SLC_FIFO_MAP_ENA + 8 + 4 + read-write + + + SLC_TXEOF_ENA + 0 + 6 + read-write + + + + + SLC_RX_EOF_DES_ADDR + 0x48 + SLC_RX_EOF_DES_ADDR + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_TX_EOF_DES_ADDR + 0x4c + SLC_TX_EOF_DES_ADDR + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_RX_EOF_BFR_DES_ADDR + 0x50 + SLC_RX_EOF_BFR_DES_ADDR + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_AHB_TEST + 0x54 + SLC_AHB_TEST + 32 + 0x00000000 + + + SLC_AHB_TESTADDR + 4 + 2 + read-write + + + SLC_AHB_TESTMODE + 0 + 3 + read-write + + + + + SLC_SDIO_ST + 0x58 + SLC_SDIO_ST + 32 + 0x00000000 + + + SLC_BUS_ST + 12 + 3 + read-write + + + SLC_SDIO_WAKEUP + 8 + 1 + read-write + + + SLC_FUNC_ST + 4 + 4 + read-write + + + SLC_CMD_ST + 0 + 3 + read-write + + + + + SLC_RX_DSCR_CONF + 0x5c + SLC_RX_DSCR_CONF + 32 + 0x00000000 + + + SLC_INFOR_NO_REPLACE + 9 + 1 + read-write + + + SLC_TOKEN_NO_REPLACE + 8 + 1 + read-write + + + + + SLC_TXLINK_DSCR + 0x60 + SLC_TXLINK_DSCR + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_TXLINK_DSCR_BF0 + 0x64 + SLC_TXLINK_DSCR_BF0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_TXLINK_DSCR_BF1 + 0x68 + SLC_TXLINK_DSCR_BF1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_RXLINK_DSCR + 0x6c + SLC_RXLINK_DSCR + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_RXLINK_DSCR_BF0 + 0x70 + SLC_RXLINK_DSCR_BF0 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_RXLINK_DSCR_BF1 + 0x74 + SLC_RXLINK_DSCR_BF1 + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_DATE + 0x78 + SLC_DATE + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + SLC_ID + 0x7c + SLC_ID + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + + + SPI0 + 0x60000200 + + 0 + 0x00000400 + registers + + + + SPI_CMD + 0x0 + In the master mode, it is the start bit of a single operation. Self-clear by hardware + + 32 + 0x00000000 + + + spi_usr + In the master mode, it is the start bit of a single operation. Self-clear by + hardware + + 18 + 1 + read-write + + spi_read311 + spi_write_enable301 + spi_write_disable291 + spi_read_id281 + spi_read_sr271 + spi_write_sr261 + spi_pp251 + spi_se241 + spi_be231 + spi_ce221 + spi_dp211 + spi_res201 + spi_hpm191 + + + + SPI_ADDR + 0x4 + In the master mode, it is the value of address in "address" phase. + 32 + 0x00000000 + + + iodata_start_addr + In the master mode, it is the value of address in "address" phase. + + 0 + 32 + read-write + + address024 + size248 + + + + SPI_CTRL + 0x8 + SPI_CTRL + 32 + 0x00000000 + + + spi_wr_bit_order + In "command", "address", "write-data" (MOSI) phases, 1: LSB first; 0: MSB + first + + 26 + 1 + read-write + + + spi_rd_bit_order + In "read-data" (MISO) phase, 1: LSB first; 0: MSB first + 25 + 1 + read-write + + + spi_qio_mode + In the read operations, "address" phase and "read-data" phase apply 4 signals + + 24 + 1 + read-write + + + spi_dio_mode + In the read operations, "address" phase and "read-data" phase apply 2 signals + + 23 + 1 + read-write + + + spi_qout_mode + In the read operations, "read-data" phase apply 4 signals + 20 + 1 + read-write + + + spi_dout_mode + In the read operations, "read-data" phase apply 2 signals + 14 + 1 + read-write + + + spi_fastrd_mode + this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and + spi_dout_mode + + 13 + 1 + read-write + + + + + SPI_RD_STATUS + 0x10 + In the slave mode, this register are the status register for the master to read out. + + 32 + 0x00000000 + + + slv_rd_status + In the slave mode, this register are the status register for the master to read + out. + + 0 + 32 + read-write + + + + + SPI_CTRL2 + 0x14 + spi_cs signal is delayed by 80MHz clock cycles + 32 + 0x00000000 + + + spi_cs_delay_num + spi_cs signal is delayed by 80MHz clock cycles + 28 + 4 + read-write + + + spi_cs_delay_mode + spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle + + 26 + 2 + read-write + + + spi_mosi_delay_num + MOSI signals are delayed by 80MHz clock cycles + 23 + 3 + read-write + + + spi_mosi_delay_mode + MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle + + 21 + 2 + read-write + + + spi_miso_delay_num + MISO signals are delayed by 80MHz clock cycles + 18 + 3 + read-write + + + spi_miso_delay_mode + MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle + + 16 + 2 + read-write + + + + + SPI_CLOCK + 0x18 + In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz + clock. + + 32 + 0x00000000 + + + spi_clk_equ_sysclk + In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 + MHz clock. + + 31 + 1 + read-write + + + spi_clkdiv_pre + In the master mode, it is pre-divider of spi_clk. + 18 + 13 + read-write + + + spi_clkcnt_N + In the master mode, it is the divider of spi_clk. So spi_clk frequency is + 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1) + + 12 + 6 + read-write + + + spi_clkcnt_H + In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, + it must be 0. + + 6 + 6 + read-write + + + spi_clkcnt_L + In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it + must be 0. + + 0 + 6 + read-write + + + + + SPI_USER + 0x1c + This bit enable the "command" phase of an operation. + 32 + 0x00000000 + + + spi_usr_command + This bit enable the "command" phase of an operation. + 31 + 1 + read-write + + + spi_usr_addr + This bit enable the "address" phase of an operation. + 30 + 1 + read-write + + + spi_usr_dummy + This bit enable the "dummy" phase of an operation. + 29 + 1 + read-write + + + spi_usr_miso + This bit enable the "read-data" phase of an operation. + 28 + 1 + read-write + + + spi_usr_mosi + This bit enable the "write-data" phase of an operation. + 27 + 1 + read-write + + + reg_usr_mosi_highpart + 1: "write-data" phase only access to high-part of the buffer spi_w8~spi_w15 + + 25 + 1 + read-write + + + reg_usr_miso_highpart + 1: "read-data" phase only access to high-part of the buffer spi_w8~spi_w15 + + 24 + 1 + read-write + + + spi_sio + 1: mosi and miso signals share the same pin + 16 + 1 + read-write + + + spi_fwrite_qio + In the write operations, "address" phase and "read-data" phase apply 4 + signals + + 15 + 1 + read-write + + + spi_fwrite_dio + In the write operations, "address" phase and "read-data" phase apply 2 + signals + + 14 + 1 + read-write + + + spi_fwrite_quad + In the write operations, "read-data" phase apply 4 signals + 13 + 1 + read-write + + + spi_fwrite_dual + In the write operations, "read-data" phase apply 2 signals + 12 + 1 + read-write + + + spi_wr_byte_order + In "command", "address", "write-data" (MOSI) phases, 1: little-endian; 0: + big_endian + + 11 + 1 + read-write + + + spi_rd_byte_order + In "read-data" (MISO) phase, 1: little-endian; 0: big_endian + 10 + 1 + read-write + + + spi_ck_i_edge + In the slave mode, 1: rising-edge; 0: falling-edge + 6 + 1 + read-write + + spi_ck_o_edgeIn the master mode, 1: rising-edge; 0: falling-edge71 + spi_cs_setupspi cs is enable when spi is in prepare phase. 1: enable 0: disable.51 + spi_cs_holdspi cs keep low when spi is in done phase. 1: enable 0: disable.41 + spi_ahb_user_commandreserved31 + spi_flash_mode21 + spi_ahb_user_command_4bytereserved11 + spi_duplexset spi in full duplex mode01 + + + + SPI_USER1 + 0x20 + The length in bits of "address" phase. The register value shall be (bit_num-1) + + 32 + 0x00000000 + + + reg_usr_addr_bitlen + The length in bits of "address" phase. The register value shall be + (bit_num-1) + + 26 + 6 + read-write + + + reg_usr_mosi_bitlen + The length in bits of "write-data" phase. The register value shall be + (bit_num-1) + + 17 + 9 + read-write + + + reg_usr_miso_bitlen + The length in bits of "read-data" phase. The register value shall be + (bit_num-1) + + 8 + 9 + read-write + + + reg_usr_dummy_cyclelen + The length in spi_clk cycles of "dummy" phase. The register value shall be + (cycle_num-1) + + 0 + 8 + read-write + + + + + SPI_USER2 + 0x24 + The length in bits of "command" phase. The register value shall be (bit_num-1) + + 32 + 0x00000000 + + + reg_usr_command_bitlen + The length in bits of "command" phase. The register value shall be + (bit_num-1) + + 28 + 4 + read-write + + + reg_usr_command_value + The value of "command" phase + 0 + 16 + read-write + + + + + SPI_WR_STATUS + 0x28 + In the slave mode, this register are the status register for the master to write + into. + + 32 + 0x00000000 + + + slv_wr_status + In the slave mode, this register are the status register for the master to + write into. + + 0 + 32 + read-write + + + + + SPI_PIN + 0x2c + 1: disable CS2; 0: spi_cs signal is from/to CS2 pin + 32 + 0x00000000 + + + spi_cs2_dis + 1: disable CS2; 0: spi_cs signal is from/to CS2 pin + 2 + 1 + read-write + + + spi_cs1_dis + 1: disable CS1; 0: spi_cs signal is from/to CS1 pin + 1 + 1 + read-write + + + spi_cs0_dis + 1: disable CS0; 0: spi_cs signal is from/to CS0 pin + 0 + 1 + read-write + + spi_idle_edgeIn the master mode, 1: high when idle; 0: low when idle291 + + + + SPI_SLAVE + 0x30 + It is the synchronous reset signal of the module. This bit is self-cleared by + hardware. + + 32 + 0x00000000 + + + spi_sync_reset + It is the synchronous reset signal of the module. This bit is self-cleared by + hardware. + + 31 + 1 + read-write + + + spi_slave_mode + 1: slave mode, 0: master mode. + 30 + 1 + read-write + + + slv_cmd_define + 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are + fixed as 1: "write-status"; 4: "read-status"; 2: "write-buffer" and 3: "read-buffer". + + 27 + 1 + read-write + + + spi_trans_cnt + The operations counter in both the master mode and the slave mode. + + 23 + 4 + read-only + + + spi_int_en + Interrupt enable bits for the below 5 sources + 5 + 5 + read-write + + + spi_trans_done + The interrupt raw bit for the completement of any operation in both the master + mode and the slave mode. + + 4 + 1 + read-write + + + slv_wr_sta_done + The interrupt raw bit for the completement of "write-status" operation in the + slave mode. + + 3 + 1 + read-write + + + slv_rd_sta_done + The interrupt raw bit for the completement of "read-status" operation in the + slave mode. + + 2 + 1 + read-write + + + slv_wr_buf_done + The interrupt raw bit for the completement of "write-buffer" operation in the + slave mode. + + 1 + 1 + read-write + + + slv_rd_buf_done + The interrupt raw bit for the completement of "read-buffer" operation in the + slave mode. + + 0 + 1 + read-write + + + + + SPI_SLAVE1 + 0x34 + In the slave mode, it is the length in bits for "write-status" and "read-status" + operations. The register valueshall be (bit_num-1) + + 32 + 0x00000000 + + + slv_status_bitlen + In the slave mode, it is the length in bits for "write-status" and + "read-status" operations. The register valueshall be (bit_num-1) + + 27 + 5 + read-write + + + slv_buf_bitlen + In the slave mode, it is the length in bits for "write-buffer" and + "read-buffer" operations. The register value shallbe (bit_num-1) + + 16 + 9 + read-write + + + slv_rd_addr_bitlen + In the slave mode, it is the address length in bits for "read-buffer" + operation. The register value shall be(bit_num-1) + + 10 + 6 + read-write + + + slv_wr_addr_bitlen + In the slave mode, it is the address length in bits for "write-buffer" + operation. The register value shall be(bit_num-1) + + 4 + 6 + read-write + + + slv_wrsta_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "write-status" + operations. + + 3 + 1 + read-write + + + slv_rdsta_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "read-status" + operations. + + 2 + 1 + read-write + + + slv_wrbuf_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "write-buffer" + operations. + + 1 + 1 + read-write + + + slv_rdbuf_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "read-buffer" + operations. + + 0 + 1 + read-write + + + + + SPI_SLAVE2 + 0x38 + In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" + operations. The registervalue shall be (cycle_num-1) + + 32 + 0x00000000 + + + slv_wrbuf_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles "dummy" phase for + "write-buffer" operations. The registervalue shall be (cycle_num-1) + + 24 + 8 + read-write + + + slv_rdbuf_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles of "dummy" phase for + "read-buffer" operations. The registervalue shall be (cycle_num-1) + + 16 + 8 + read-write + + + slv_wrsta_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles of "dummy" phase for + "write-status" operations. Theregister value shall be (cycle_num-1) + + 8 + 8 + read-write + + + slv_rdsta_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles of "dummy" phase for + "read-status" operations. Theregister value shall be (cycle_num-1) + + 0 + 8 + read-write + + + + + SPI_SLAVE3 + 0x3c + In slave mode, it is the value of "write-status" command + 32 + 0x00000000 + + + slv_wrsta_cmd_value + In slave mode, it is the value of "write-status" command + 24 + 8 + read-write + + + slv_rdsta_cmd_value + In slave mode, it is the value of "read-status" command + 16 + 8 + read-write + + + slv_wrbuf_cmd_value + In slave mode, it is the value of "write-buffer" command + 8 + 8 + read-write + + + slv_rdbuf_cmd_value + In slave mode, it is the value of "read-buffer" command + 0 + 8 + read-write + + + + + SPI_EXT3 + 0xfc + This register is for two SPI masters to share the same cs, clock and data signals. + + 32 + 0x00000000 + + + reg_int_hold_ena + This register is for two SPI masters to share the same cs, clock and data + signals. + + 0 + 2 + read-write + + + + + SPI_W0 + 0x40 + the data inside the buffer of the SPI module, byte 0 + 32 + 0x00000000 + + + spi_w0 + the data inside the buffer of the SPI module, byte 0 + 0 + 32 + read-write + + + + + SPI_W1 + 0x60 + the data inside the buffer of the SPI module, byte 1 + 32 + 0x00000000 + + + spi_w1 + the data inside the buffer of the SPI module, byte 1 + 0 + 32 + read-write + + + + + SPI_W2 + 0x80 + the data inside the buffer of the SPI module, byte 2 + 32 + 0x00000000 + + + spi_w2 + the data inside the buffer of the SPI module, byte 2 + 0 + 32 + read-write + + + + + SPI_W3 + 0xa0 + the data inside the buffer of the SPI module, byte 3 + 32 + 0x00000000 + + + spi_w3 + the data inside the buffer of the SPI module, byte 3 + 0 + 32 + read-write + + + + + SPI_W4 + 0xc0 + the data inside the buffer of the SPI module, byte 4 + 32 + 0x00000000 + + + spi_w4 + the data inside the buffer of the SPI module, byte 4 + 0 + 32 + read-write + + + + + SPI_W5 + 0xe0 + the data inside the buffer of the SPI module, byte 5 + 32 + 0x00000000 + + + spi_w5 + the data inside the buffer of the SPI module, byte 5 + 0 + 32 + read-write + + + + + SPI_W6 + 0x100 + the data inside the buffer of the SPI module, byte 6 + 32 + 0x00000000 + + + spi_w6 + the data inside the buffer of the SPI module, byte 6 + 0 + 32 + read-write + + + + + SPI_W7 + 0x120 + the data inside the buffer of the SPI module, byte 7 + 32 + 0x00000000 + + + spi_w7 + the data inside the buffer of the SPI module, byte 7 + 0 + 32 + read-write + + + + + SPI_W8 + 0x140 + the data inside the buffer of the SPI module, byte 8 + 32 + 0x00000000 + + + spi_w8 + the data inside the buffer of the SPI module, byte 8 + 0 + 32 + read-write + + + + + SPI_W9 + 0x160 + the data inside the buffer of the SPI module, byte 9 + 32 + 0x00000000 + + + spi_w9 + the data inside the buffer of the SPI module, byte 9 + 0 + 32 + read-write + + + + + SPI_W10 + 0x180 + the data inside the buffer of the SPI module, byte 10 + 32 + 0x00000000 + + + spi_w10 + the data inside the buffer of the SPI module, byte 10 + 0 + 32 + read-write + + + + + SPI_W11 + 0x1a0 + the data inside the buffer of the SPI module, byte 11 + 32 + 0x00000000 + + + spi_w11 + the data inside the buffer of the SPI module, byte 11 + 0 + 32 + read-write + + + + + SPI_W12 + 0x1c0 + the data inside the buffer of the SPI module, byte 12 + 32 + 0x00000000 + + + spi_w12 + the data inside the buffer of the SPI module, byte 12 + 0 + 32 + read-write + + + + + SPI_W13 + 0x1e0 + the data inside the buffer of the SPI module, byte 13 + 32 + 0x00000000 + + + spi_w13 + the data inside the buffer of the SPI module, byte 13 + 0 + 32 + read-write + + + + + SPI_W14 + 0x200 + the data inside the buffer of the SPI module, byte 14 + 32 + 0x00000000 + + + spi_w14 + the data inside the buffer of the SPI module, byte 14 + 0 + 32 + read-write + + + + + SPI_W15 + 0x220 + the data inside the buffer of the SPI module, byte 15 + 32 + 0x00000000 + + + spi_w15 + the data inside the buffer of the SPI module, byte 15 + 0 + 32 + read-write + + + + SPI_CTRL1statusIn the slave mode, it is the status for master to read out.016 + wb_modeMode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.168 + status_extIn the slave mode,it is the status for master to read out.248 + 1232read-write0 + + + + SPI1 + 0x60000100 + + 0 + 0x00000400 + registers + + + + SPI_CMD + 0x0 + In the master mode, it is the start bit of a single operation. Self-clear by hardware + + 32 + 0x00000000 + + + spi_usr + In the master mode, it is the start bit of a single operation. Self-clear by + hardware + + 18 + 1 + read-write + + spi_read311 + spi_write_enable301 + spi_write_disable291 + spi_read_id281 + spi_read_sr271 + spi_write_sr261 + spi_pp251 + spi_se241 + spi_be231 + spi_ce221 + spi_dp211 + spi_res201 + spi_hpm191 + + + + SPI_ADDR + 0x4 + In the master mode, it is the value of address in "address" phase. + 32 + 0x00000000 + + + iodata_start_addr + In the master mode, it is the value of address in "address" phase. + + 0 + 32 + read-write + + address024 + size248 + + + + SPI_CTRL + 0x8 + SPI_CTRL + 32 + 0x00000000 + + + spi_wr_bit_order + In "command", "address", "write-data" (MOSI) phases, 1: LSB first; 0: MSB + first + + 26 + 1 + read-write + + + spi_rd_bit_order + In "read-data" (MISO) phase, 1: LSB first; 0: MSB first + 25 + 1 + read-write + + + spi_qio_mode + In the read operations, "address" phase and "read-data" phase apply 4 signals + + 24 + 1 + read-write + + + spi_dio_mode + In the read operations, "address" phase and "read-data" phase apply 2 signals + + 23 + 1 + read-write + + + spi_qout_mode + In the read operations, "read-data" phase apply 4 signals + 20 + 1 + read-write + + + spi_dout_mode + In the read operations, "read-data" phase apply 2 signals + 14 + 1 + read-write + + + spi_fastrd_mode + this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and + spi_dout_mode + + 13 + 1 + read-write + + + + + SPI_RD_STATUS + 0x10 + In the slave mode, this register are the status register for the master to read out. + + 32 + 0x00000000 + + + slv_rd_status + In the slave mode, this register are the status register for the master to read + out. + + 0 + 32 + read-write + + + + + SPI_CTRL2 + 0x14 + spi_cs signal is delayed by 80MHz clock cycles + 32 + 0x00000000 + + + spi_cs_delay_num + spi_cs signal is delayed by 80MHz clock cycles + 28 + 4 + read-write + + + spi_cs_delay_mode + spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle + + 26 + 2 + read-write + + + spi_mosi_delay_num + MOSI signals are delayed by 80MHz clock cycles + 23 + 3 + read-write + + + spi_mosi_delay_mode + MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle + + 21 + 2 + read-write + + + spi_miso_delay_num + MISO signals are delayed by 80MHz clock cycles + 18 + 3 + read-write + + + spi_miso_delay_mode + MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle + + 16 + 2 + read-write + + + + + SPI_CLOCK + 0x18 + In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz + clock. + + 32 + 0x00000000 + + + spi_clk_equ_sysclk + In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 + MHz clock. + + 31 + 1 + read-write + + + spi_clkdiv_pre + In the master mode, it is pre-divider of spi_clk. + 18 + 13 + read-write + + + spi_clkcnt_N + In the master mode, it is the divider of spi_clk. So spi_clk frequency is + 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1) + + 12 + 6 + read-write + + + spi_clkcnt_H + In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, + it must be 0. + + 6 + 6 + read-write + + + spi_clkcnt_L + In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it + must be 0. + + 0 + 6 + read-write + + + + + SPI_USER + 0x1c + This bit enable the "command" phase of an operation. + 32 + 0x00000000 + + + spi_usr_command + This bit enable the "command" phase of an operation. + 31 + 1 + read-write + + + spi_usr_addr + This bit enable the "address" phase of an operation. + 30 + 1 + read-write + + + spi_usr_dummy + This bit enable the "dummy" phase of an operation. + 29 + 1 + read-write + + + spi_usr_miso + This bit enable the "read-data" phase of an operation. + 28 + 1 + read-write + + + spi_usr_mosi + This bit enable the "write-data" phase of an operation. + 27 + 1 + read-write + + + reg_usr_mosi_highpart + 1: "write-data" phase only access to high-part of the buffer spi_w8~spi_w15 + + 25 + 1 + read-write + + + reg_usr_miso_highpart + 1: "read-data" phase only access to high-part of the buffer spi_w8~spi_w15 + + 24 + 1 + read-write + + + spi_sio + 1: mosi and miso signals share the same pin + 16 + 1 + read-write + + + spi_fwrite_qio + In the write operations, "address" phase and "read-data" phase apply 4 + signals + + 15 + 1 + read-write + + + spi_fwrite_dio + In the write operations, "address" phase and "read-data" phase apply 2 + signals + + 14 + 1 + read-write + + + spi_fwrite_quad + In the write operations, "read-data" phase apply 4 signals + 13 + 1 + read-write + + + spi_fwrite_dual + In the write operations, "read-data" phase apply 2 signals + 12 + 1 + read-write + + + spi_wr_byte_order + In "command", "address", "write-data" (MOSI) phases, 1: little-endian; 0: + big_endian + + 11 + 1 + read-write + + + spi_rd_byte_order + In "read-data" (MISO) phase, 1: little-endian; 0: big_endian + 10 + 1 + read-write + + + spi_ck_i_edge + In the slave mode, 1: rising-edge; 0: falling-edge + 6 + 1 + read-write + + spi_ck_o_edgeIn the master mode, 1: rising-edge; 0: falling-edge71 + spi_cs_setupspi cs is enable when spi is in prepare phase. 1: enable 0: disable.51 + spi_cs_holdspi cs keep low when spi is in done phase. 1: enable 0: disable.41 + spi_ahb_user_commandreserved31 + spi_flash_mode21 + spi_ahb_user_command_4bytereserved11 + spi_duplexset spi in full duplex mode01 + + + + SPI_USER1 + 0x20 + The length in bits of "address" phase. The register value shall be (bit_num-1) + + 32 + 0x00000000 + + + reg_usr_addr_bitlen + The length in bits of "address" phase. The register value shall be + (bit_num-1) + + 26 + 6 + read-write + + + reg_usr_mosi_bitlen + The length in bits of "write-data" phase. The register value shall be + (bit_num-1) + + 17 + 9 + read-write + + + reg_usr_miso_bitlen + The length in bits of "read-data" phase. The register value shall be + (bit_num-1) + + 8 + 9 + read-write + + + reg_usr_dummy_cyclelen + The length in spi_clk cycles of "dummy" phase. The register value shall be + (cycle_num-1) + + 0 + 8 + read-write + + + + + SPI_USER2 + 0x24 + The length in bits of "command" phase. The register value shall be (bit_num-1) + + 32 + 0x00000000 + + + reg_usr_command_bitlen + The length in bits of "command" phase. The register value shall be + (bit_num-1) + + 28 + 4 + read-write + + + reg_usr_command_value + The value of "command" phase + 0 + 16 + read-write + + + + + SPI_WR_STATUS + 0x28 + In the slave mode, this register are the status register for the master to write + into. + + 32 + 0x00000000 + + + slv_wr_status + In the slave mode, this register are the status register for the master to + write into. + + 0 + 32 + read-write + + + + + SPI_PIN + 0x2c + 1: disable CS2; 0: spi_cs signal is from/to CS2 pin + 32 + 0x00000000 + + + spi_cs2_dis + 1: disable CS2; 0: spi_cs signal is from/to CS2 pin + 2 + 1 + read-write + + + spi_cs1_dis + 1: disable CS1; 0: spi_cs signal is from/to CS1 pin + 1 + 1 + read-write + + + spi_cs0_dis + 1: disable CS0; 0: spi_cs signal is from/to CS0 pin + 0 + 1 + read-write + + spi_idle_edgeIn the master mode, 1: high when idle; 0: low when idle291 + + + + SPI_SLAVE + 0x30 + It is the synchronous reset signal of the module. This bit is self-cleared by + hardware. + + 32 + 0x00000000 + + + spi_sync_reset + It is the synchronous reset signal of the module. This bit is self-cleared by + hardware. + + 31 + 1 + read-write + + + spi_slave_mode + 1: slave mode, 0: master mode. + 30 + 1 + read-write + + + slv_cmd_define + 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are + fixed as 1: "write-status"; 4: "read-status"; 2: "write-buffer" and 3: "read-buffer". + + 27 + 1 + read-write + + + spi_trans_cnt + The operations counter in both the master mode and the slave mode. + + 23 + 4 + read-only + + + spi_int_en + Interrupt enable bits for the below 5 sources + 5 + 5 + read-write + + + spi_trans_done + The interrupt raw bit for the completement of any operation in both the master + mode and the slave mode. + + 4 + 1 + read-write + + + slv_wr_sta_done + The interrupt raw bit for the completement of "write-status" operation in the + slave mode. + + 3 + 1 + read-write + + + slv_rd_sta_done + The interrupt raw bit for the completement of "read-status" operation in the + slave mode. + + 2 + 1 + read-write + + + slv_wr_buf_done + The interrupt raw bit for the completement of "write-buffer" operation in the + slave mode. + + 1 + 1 + read-write + + + slv_rd_buf_done + The interrupt raw bit for the completement of "read-buffer" operation in the + slave mode. + + 0 + 1 + read-write + + + + + SPI_SLAVE1 + 0x34 + In the slave mode, it is the length in bits for "write-status" and "read-status" + operations. The register valueshall be (bit_num-1) + + 32 + 0x00000000 + + + slv_status_bitlen + In the slave mode, it is the length in bits for "write-status" and + "read-status" operations. The register valueshall be (bit_num-1) + + 27 + 5 + read-write + + + slv_buf_bitlen + In the slave mode, it is the length in bits for "write-buffer" and + "read-buffer" operations. The register value shallbe (bit_num-1) + + 16 + 9 + read-write + + + slv_rd_addr_bitlen + In the slave mode, it is the address length in bits for "read-buffer" + operation. The register value shall be(bit_num-1) + + 10 + 6 + read-write + + + slv_wr_addr_bitlen + In the slave mode, it is the address length in bits for "write-buffer" + operation. The register value shall be(bit_num-1) + + 4 + 6 + read-write + + + slv_wrsta_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "write-status" + operations. + + 3 + 1 + read-write + + + slv_rdsta_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "read-status" + operations. + + 2 + 1 + read-write + + + slv_wrbuf_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "write-buffer" + operations. + + 1 + 1 + read-write + + + slv_rdbuf_dummy_en + In the slave mode, it is the enable bit of "dummy" phase for "read-buffer" + operations. + + 0 + 1 + read-write + + + + + SPI_SLAVE2 + 0x38 + In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" + operations. The registervalue shall be (cycle_num-1) + + 32 + 0x00000000 + + + slv_wrbuf_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles "dummy" phase for + "write-buffer" operations. The registervalue shall be (cycle_num-1) + + 24 + 8 + read-write + + + slv_rdbuf_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles of "dummy" phase for + "read-buffer" operations. The registervalue shall be (cycle_num-1) + + 16 + 8 + read-write + + + slv_wrsta_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles of "dummy" phase for + "write-status" operations. Theregister value shall be (cycle_num-1) + + 8 + 8 + read-write + + + slv_rdsta_dummy_cyclelen + In the slave mode, it is the length in spi_clk cycles of "dummy" phase for + "read-status" operations. Theregister value shall be (cycle_num-1) + + 0 + 8 + read-write + + + + + SPI_SLAVE3 + 0x3c + In slave mode, it is the value of "write-status" command + 32 + 0x00000000 + + + slv_wrsta_cmd_value + In slave mode, it is the value of "write-status" command + 24 + 8 + read-write + + + slv_rdsta_cmd_value + In slave mode, it is the value of "read-status" command + 16 + 8 + read-write + + + slv_wrbuf_cmd_value + In slave mode, it is the value of "write-buffer" command + 8 + 8 + read-write + + + slv_rdbuf_cmd_value + In slave mode, it is the value of "read-buffer" command + 0 + 8 + read-write + + + + + SPI_EXT3 + 0xfc + This register is for two SPI masters to share the same cs, clock and data signals. + + 32 + 0x00000000 + + + reg_int_hold_ena + This register is for two SPI masters to share the same cs, clock and data + signals. + + 0 + 2 + read-write + + + + + SPI_W0 + 0x40 + the data inside the buffer of the SPI module, byte 0 + 32 + 0x00000000 + + + spi_w0 + the data inside the buffer of the SPI module, byte 0 + 0 + 32 + read-write + + + + + SPI_W1 + 0x60 + the data inside the buffer of the SPI module, byte 1 + 32 + 0x00000000 + + + spi_w1 + the data inside the buffer of the SPI module, byte 1 + 0 + 32 + read-write + + + + + SPI_W2 + 0x80 + the data inside the buffer of the SPI module, byte 2 + 32 + 0x00000000 + + + spi_w2 + the data inside the buffer of the SPI module, byte 2 + 0 + 32 + read-write + + + + + SPI_W3 + 0xa0 + the data inside the buffer of the SPI module, byte 3 + 32 + 0x00000000 + + + spi_w3 + the data inside the buffer of the SPI module, byte 3 + 0 + 32 + read-write + + + + + SPI_W4 + 0xc0 + the data inside the buffer of the SPI module, byte 4 + 32 + 0x00000000 + + + spi_w4 + the data inside the buffer of the SPI module, byte 4 + 0 + 32 + read-write + + + + + SPI_W5 + 0xe0 + the data inside the buffer of the SPI module, byte 5 + 32 + 0x00000000 + + + spi_w5 + the data inside the buffer of the SPI module, byte 5 + 0 + 32 + read-write + + + + + SPI_W6 + 0x100 + the data inside the buffer of the SPI module, byte 6 + 32 + 0x00000000 + + + spi_w6 + the data inside the buffer of the SPI module, byte 6 + 0 + 32 + read-write + + + + + SPI_W7 + 0x120 + the data inside the buffer of the SPI module, byte 7 + 32 + 0x00000000 + + + spi_w7 + the data inside the buffer of the SPI module, byte 7 + 0 + 32 + read-write + + + + + SPI_W8 + 0x140 + the data inside the buffer of the SPI module, byte 8 + 32 + 0x00000000 + + + spi_w8 + the data inside the buffer of the SPI module, byte 8 + 0 + 32 + read-write + + + + + SPI_W9 + 0x160 + the data inside the buffer of the SPI module, byte 9 + 32 + 0x00000000 + + + spi_w9 + the data inside the buffer of the SPI module, byte 9 + 0 + 32 + read-write + + + + + SPI_W10 + 0x180 + the data inside the buffer of the SPI module, byte 10 + 32 + 0x00000000 + + + spi_w10 + the data inside the buffer of the SPI module, byte 10 + 0 + 32 + read-write + + + + + SPI_W11 + 0x1a0 + the data inside the buffer of the SPI module, byte 11 + 32 + 0x00000000 + + + spi_w11 + the data inside the buffer of the SPI module, byte 11 + 0 + 32 + read-write + + + + + SPI_W12 + 0x1c0 + the data inside the buffer of the SPI module, byte 12 + 32 + 0x00000000 + + + spi_w12 + the data inside the buffer of the SPI module, byte 12 + 0 + 32 + read-write + + + + + SPI_W13 + 0x1e0 + the data inside the buffer of the SPI module, byte 13 + 32 + 0x00000000 + + + spi_w13 + the data inside the buffer of the SPI module, byte 13 + 0 + 32 + read-write + + + + + SPI_W14 + 0x200 + the data inside the buffer of the SPI module, byte 14 + 32 + 0x00000000 + + + spi_w14 + the data inside the buffer of the SPI module, byte 14 + 0 + 32 + read-write + + + + + SPI_W15 + 0x220 + the data inside the buffer of the SPI module, byte 15 + 32 + 0x00000000 + + + spi_w15 + the data inside the buffer of the SPI module, byte 15 + 0 + 32 + read-write + + + + SPI_CTRL1statusIn the slave mode, it is the status for master to read out.016 + wb_modeMode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.168 + status_extIn the slave mode,it is the status for master to read out.248 + 1232read-write0 + + + + TIMER + 0x60000600 + + 0 + 0x00000120 + registers + + + + FRC1_LOAD + 0x0 + the load value into the counter + 32 + 0x00000000 + + + frc1_load_value + the load value into the counter + 0 + 23 + read-write + + + + + FRC1_COUNT + 0x4 + the current value of the counter. It is a decreasingcounter. + 32 + 0x00000000 + + + frc1_count + the current value of the counter. It is a decreasingcounter. + 0 + 23 + read-only + + + + + FRC1_CTRL + 0x8 + FRC1_CTRL + 32 + 0x00000000 + + + frc1_int + the status of the interrupt, when the count isdereased to zero + 8 + 1 + read-only + + + frc1_ctrl + bit[7]: timer enable, bit[6]: automatically reload, when the counter isequal to + zero, bit[3:2]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by + 256, bit[0]: interrupt type, 0:edge, 1:level + + 0 + 8 + read-write + + timer_enableEnable or disable the timer71read-write + rolloverAutomatically reload when the counter hits zero61read-write + prescale_dividerPre-scale divider for the timer22read-writeprescale_dividerread-writedevided_by_1divided by 10devided_by_16divided by 161devided_by_256divided by 2562 + + interrupt_typeConfigure the interrupt type01read-writeinterrupt_typeread-writeedgeedge0levellevel1 + + + + + FRC1_INT + 0xc + FRC1_INT + 32 + 0x00000000 + + + frc1_int_clr_mask + write to clear the status of the interrupt, if theinterrupt type is "level" + + 0 + 1 + read-write + + + + + FRC2_LOAD + 0x20 + the load value into the counter + 32 + 0x00000000 + + + frc2_load_value + the load value into the counter + 0 + 32 + read-write + + + + + FRC2_COUNT + 0x24 + the current value of the counter. It is a increasingcounter. + 32 + 0x00000000 + + + frc2_count + the current value of the counter. It is a increasingcounter. + 0 + 32 + read-only + + + + + FRC2_CTRL + 0x28 + FRC2_CTRL + 32 + 0x00000000 + + + frc2_int + the status of the interrupt, when the count is equal tothe alarm value + + 8 + 1 + read-only + + + frc2_ctrl + bit[7]: timer enable, bit[6]: automatically reload, when the counter isequal to + zero, bit[3:2]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by + 256, bit[0]: interrupt type, 0:edge, 1:level + + 0 + 8 + read-write + + timer_enableEnable or disable the timer71read-write + rolloverAutomatically reload when the counter hits zero61read-write + prescale_dividerPre-scale divider for the timer22read-writeprescale_dividerread-writedevided_by_1divided by 10devided_by_16divided by 161devided_by_256divided by 2562 + + interrupt_typeConfigure the interrupt type01read-writeinterrupt_typeread-writeedgeedge0levellevel1 + + + + + FRC2_INT + 0x2c + FRC2_INT + 32 + 0x00000000 + + + frc2_int_clr_mask + write to clear the status of the interrupt, if theinterrupt type is "level" + + 0 + 1 + read-write + + + + + FRC2_ALARM + 0x30 + the alarm value for the counter + 32 + 0x00000000 + + + frc2_alarm + the alarm value for the counter + 0 + 32 + read-write + + + + + + + UART0 + 0x60000000 + + 0 + 0x000001e0 + registers + + + + UART_FIFO + 0x0 + UART FIFO,length 128 + 32 + 0x00000000 + + + rxfifo_rd_byte + R/W share the same address + 0 + 8 + read-only + + rxfifo_write_byteR/W share the same address08 + + + + UART_INT_RAW + 0x4 + UART INTERRUPT RAW STATE + 32 + 0x00000000 + + + rxfifo_tout_int_raw + The interrupt raw bit for Rx time-out interrupt(depands on + theUART_RX_TOUT_THRHD) + + 8 + 1 + read-only + + + brk_det_int_raw + The interrupt raw bit for Rx byte start error + 7 + 1 + read-only + + + cts_chg_int_raw + The interrupt raw bit for CTS changing level + 6 + 1 + read-only + + + dsr_chg_int_raw + The interrupt raw bit for DSR changing level + 5 + 1 + read-only + + + rxfifo_ovf_int_raw + The interrupt raw bit for rx fifo overflow + 4 + 1 + read-only + + + frm_err_int_raw + The interrupt raw bit for other rx error + 3 + 1 + read-only + + + parity_err_int_raw + The interrupt raw bit for parity check error + 2 + 1 + read-only + + + txfifo_empty_int_raw + The interrupt raw bit for tx fifo empty interrupt(depands + onUART_TXFIFO_EMPTY_THRHD bits) + + 1 + 1 + read-only + + + rxfifo_full_int_raw + The interrupt raw bit for rx fifo full interrupt(depands + onUART_RXFIFO_FULL_THRHD bits) + + 0 + 1 + read-only + + + + + UART_INT_ST + 0x8 + UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA + 32 + 0x00000000 + + + rxfifo_tout_int_st + The interrupt state bit for Rx time-out event + 8 + 1 + read-only + + + brk_det_int_st + The interrupt state bit for rx byte start error + 7 + 1 + read-only + + + cts_chg_int_st + The interrupt state bit for CTS changing level + 6 + 1 + read-only + + + dsr_chg_int_st + The interrupt state bit for DSR changing level + 5 + 1 + read-only + + + rxfifo_ovf_int_st + The interrupt state bit for RX fifo overflow + 4 + 1 + read-only + + + frm_err_int_st + The interrupt state for other rx error + 3 + 1 + read-only + + + parity_err_int_st + The interrupt state bit for rx parity error + 2 + 1 + read-only + + + txfifo_empty_int_st + The interrupt state bit for TX fifo empty + 1 + 1 + read-only + + + rxfifo_full_int_st + The interrupt state bit for RX fifo full event + 0 + 1 + read-only + + + + + UART_INT_ENA + 0xc + UART INTERRUPT ENABLE REGISTER + 32 + 0x00000000 + + + rxfifo_tout_int_ena + The interrupt enable bit for rx time-out interrupt + 8 + 1 + read-write + + + brk_det_int_ena + The interrupt enable bit for rx byte start error + 7 + 1 + read-write + + + cts_chg_int_ena + The interrupt enable bit for CTS changing level + 6 + 1 + read-write + + + dsr_chg_int_ena + The interrupt enable bit for DSR changing level + 5 + 1 + read-write + + + rxfifo_ovf_int_ena + The interrupt enable bit for rx fifo overflow + 4 + 1 + read-write + + + frm_err_int_ena + The interrupt enable bit for other rx error + 3 + 1 + read-write + + + parity_err_int_ena + The interrupt enable bit for parity error + 2 + 1 + read-write + + + txfifo_empty_int_ena + The interrupt enable bit for tx fifo empty event + 1 + 1 + read-write + + + rxfifo_full_int_ena + The interrupt enable bit for rx fifo full event + 0 + 1 + read-write + + + + + UART_INT_CLR + 0x10 + UART INTERRUPT CLEAR REGISTER + 32 + 0x00000000 + + + rxfifo_tout_int_clr + Set this bit to clear the rx time-out interrupt + 8 + 1 + write-only + + + brk_det_int_clr + Set this bit to clear the rx byte start interrupt + 7 + 1 + write-only + + + cts_chg_int_clr + Set this bit to clear the CTS changing interrupt + 6 + 1 + write-only + + + dsr_chg_int_clr + Set this bit to clear the DSR changing interrupt + 5 + 1 + write-only + + + rxfifo_ovf_int_clr + Set this bit to clear the rx fifo over-flow interrupt + 4 + 1 + write-only + + + frm_err_int_clr + Set this bit to clear other rx error interrupt + 3 + 1 + write-only + + + parity_err_int_clr + Set this bit to clear the parity error interrupt + 2 + 1 + write-only + + + txfifo_empty_int_clr + Set this bit to clear the tx fifo empty interrupt + 1 + 1 + write-only + + + rxfifo_full_int_clr + Set this bit to clear the rx fifo full interrupt + 0 + 1 + write-only + + + + + UART_CLKDIV + 0x14 + UART CLK DIV REGISTER + 32 + 0x00000000 + + + uart_clkdiv + BAUDRATE = UART_CLK_FREQ / UART_CLKDIV + 0 + 20 + read-write + + + + + UART_AUTOBAUD + 0x18 + UART BAUDRATE DETECT REGISTER + 32 + 0x00000000 + + + glitch_filt + 8 + 8 + read-write + + + autobaud_en + Set this bit to enable baudrate detect + 0 + 1 + read-write + + + + + UART_STATUS + 0x1c + UART STATUS REGISTER + 32 + 0x00000000 + + + txd + The level of the uart txd pin + 31 + 1 + read-only + + + rtsn + The level of uart rts pin + 30 + 1 + read-only + + + dtrn + The level of uart dtr pin + 29 + 1 + read-only + + + txfifo_cnt + Number of data in UART TX fifo + 16 + 8 + read-only + + + rxd + The level of uart rxd pin + 15 + 1 + read-only + + + ctsn + The level of uart cts pin + 14 + 1 + read-only + + + dsrn + The level of uart dsr pin + 13 + 1 + read-only + + + rxfifo_cnt + Number of data in uart rx fifo + 0 + 8 + read-only + + + + + UART_CONF0 + 0x20 + UART CONFIG0(UART0 and UART1) + 32 + 0x00000000 + + + uart_dtr_inv + Set this bit to inverse uart dtr level + 24 + 1 + read-write + + + uart_rts_inv + Set this bit to inverse uart rts level + 23 + 1 + read-write + + + uart_txd_inv + Set this bit to inverse uart txd level + 22 + 1 + read-write + + + uart_dsr_inv + Set this bit to inverse uart dsr level + 21 + 1 + read-write + + + uart_cts_inv + Set this bit to inverse uart cts level + 20 + 1 + read-write + + + uart_rxd_inv + Set this bit to inverse uart rxd level + 19 + 1 + read-write + + + txfifo_rst + Set this bit to reset uart tx fifo + 18 + 1 + read-write + + + rxfifo_rst + Set this bit to reset uart rx fifo + 17 + 1 + read-write + + + tx_flow_en + Set this bit to enable uart tx hardware flow control + 15 + 1 + read-write + + + uart_loopback + Set this bit to enable uart loopback test mode + 14 + 1 + read-write + + + txd_brk + RESERVED, DO NOT CHANGE THIS BIT + 8 + 1 + read-write + + + sw_dtr + sw dtr + 7 + 1 + read-write + + + sw_rts + sw rts + 6 + 1 + read-write + + + stop_bit_num + Set stop bit: 1:1bit 2:1.5bits 3:2bits + 4 + 2 + read-write + + + bit_num + Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits + 2 + 2 + read-write + + + parity_en + Set this bit to enable uart parity check + 1 + 1 + read-write + + + parity + Set parity check: 0:even 1:odd, UART CONFIG1 + 0 + 1 + read-write + + + + + UART_CONF1 + 0x24 + Set this bit to enable rx time-out function + 32 + 0x00000000 + + + rx_tout_en + Set this bit to enable rx time-out function + 31 + 1 + read-write + + + rx_tout_thrhd + Config bits for rx time-out threshold,uint: byte,0-127 + 24 + 7 + read-write + + + rx_flow_en + Set this bit to enable rx hardware flow control + 23 + 1 + read-write + + + rx_flow_thrhd + The config bits for rx flow control threshold,0-127 + 16 + 7 + read-write + + + txfifo_empty_thrhd + The config bits for tx fifo empty threshold,0-127 + 8 + 7 + read-write + + + rxfifo_full_thrhd + The config bits for rx fifo full threshold,0-127 + 0 + 7 + read-write + + + + + UART_LOWPULSE + 0x28 + UART_LOWPULSE + 32 + 0x00000000 + + + lowpulse_min_cnt + used in baudrate detect + 0 + 20 + read-only + + + + + UART_HIGHPULSE + 0x2c + UART_HIGHPULSE + 32 + 0x00000000 + + + highpulse_min_cnt + used in baudrate detect + 0 + 20 + read-only + + + + + UART_RXD_CNT + 0x30 + UART_RXD_CNT + 32 + 0x00000000 + + + rxd_edge_cnt + used in baudrate detect + 0 + 10 + read-only + + + + + UART_DATE + 0x78 + UART HW INFO + 32 + 0x00000000 + + + uart_date + UART HW INFO + 0 + 32 + read-write + + + + + UART_ID + 0x7c + UART_ID + 32 + 0x00000000 + + + uart_id + 0 + 32 + read-write + + + + + + + UART1 + 0x60000f00 + + 0 + 0x000001e0 + registers + + + + UART_FIFO + 0x0 + UART FIFO,length 128 + 32 + 0x00000000 + + + rxfifo_rd_byte + R/W share the same address + 0 + 8 + read-only + + rxfifo_write_byteR/W share the same address08 + + + + UART_INT_RAW + 0x4 + UART INTERRUPT RAW STATE + 32 + 0x00000000 + + + rxfifo_tout_int_raw + The interrupt raw bit for Rx time-out interrupt(depands on + theUART_RX_TOUT_THRHD) + + 8 + 1 + read-only + + + brk_det_int_raw + The interrupt raw bit for Rx byte start error + 7 + 1 + read-only + + + cts_chg_int_raw + The interrupt raw bit for CTS changing level + 6 + 1 + read-only + + + dsr_chg_int_raw + The interrupt raw bit for DSR changing level + 5 + 1 + read-only + + + rxfifo_ovf_int_raw + The interrupt raw bit for rx fifo overflow + 4 + 1 + read-only + + + frm_err_int_raw + The interrupt raw bit for other rx error + 3 + 1 + read-only + + + parity_err_int_raw + The interrupt raw bit for parity check error + 2 + 1 + read-only + + + txfifo_empty_int_raw + The interrupt raw bit for tx fifo empty interrupt(depands + onUART_TXFIFO_EMPTY_THRHD bits) + + 1 + 1 + read-only + + + rxfifo_full_int_raw + The interrupt raw bit for rx fifo full interrupt(depands + onUART_RXFIFO_FULL_THRHD bits) + + 0 + 1 + read-only + + + + + UART_INT_ST + 0x8 + UART INTERRUPT STATEREGISTERUART_INT_RAW&UART_INT_ENA + 32 + 0x00000000 + + + rxfifo_tout_int_st + The interrupt state bit for Rx time-out event + 8 + 1 + read-only + + + brk_det_int_st + The interrupt state bit for rx byte start error + 7 + 1 + read-only + + + cts_chg_int_st + The interrupt state bit for CTS changing level + 6 + 1 + read-only + + + dsr_chg_int_st + The interrupt state bit for DSR changing level + 5 + 1 + read-only + + + rxfifo_ovf_int_st + The interrupt state bit for RX fifo overflow + 4 + 1 + read-only + + + frm_err_int_st + The interrupt state for other rx error + 3 + 1 + read-only + + + parity_err_int_st + The interrupt state bit for rx parity error + 2 + 1 + read-only + + + txfifo_empty_int_st + The interrupt state bit for TX fifo empty + 1 + 1 + read-only + + + rxfifo_full_int_st + The interrupt state bit for RX fifo full event + 0 + 1 + read-only + + + + + UART_INT_ENA + 0xc + UART INTERRUPT ENABLE REGISTER + 32 + 0x00000000 + + + rxfifo_tout_int_ena + The interrupt enable bit for rx time-out interrupt + 8 + 1 + read-write + + + brk_det_int_ena + The interrupt enable bit for rx byte start error + 7 + 1 + read-write + + + cts_chg_int_ena + The interrupt enable bit for CTS changing level + 6 + 1 + read-write + + + dsr_chg_int_ena + The interrupt enable bit for DSR changing level + 5 + 1 + read-write + + + rxfifo_ovf_int_ena + The interrupt enable bit for rx fifo overflow + 4 + 1 + read-write + + + frm_err_int_ena + The interrupt enable bit for other rx error + 3 + 1 + read-write + + + parity_err_int_ena + The interrupt enable bit for parity error + 2 + 1 + read-write + + + txfifo_empty_int_ena + The interrupt enable bit for tx fifo empty event + 1 + 1 + read-write + + + rxfifo_full_int_ena + The interrupt enable bit for rx fifo full event + 0 + 1 + read-write + + + + + UART_INT_CLR + 0x10 + UART INTERRUPT CLEAR REGISTER + 32 + 0x00000000 + + + rxfifo_tout_int_clr + Set this bit to clear the rx time-out interrupt + 8 + 1 + write-only + + + brk_det_int_clr + Set this bit to clear the rx byte start interrupt + 7 + 1 + write-only + + + cts_chg_int_clr + Set this bit to clear the CTS changing interrupt + 6 + 1 + write-only + + + dsr_chg_int_clr + Set this bit to clear the DSR changing interrupt + 5 + 1 + write-only + + + rxfifo_ovf_int_clr + Set this bit to clear the rx fifo over-flow interrupt + 4 + 1 + write-only + + + frm_err_int_clr + Set this bit to clear other rx error interrupt + 3 + 1 + write-only + + + parity_err_int_clr + Set this bit to clear the parity error interrupt + 2 + 1 + write-only + + + txfifo_empty_int_clr + Set this bit to clear the tx fifo empty interrupt + 1 + 1 + write-only + + + rxfifo_full_int_clr + Set this bit to clear the rx fifo full interrupt + 0 + 1 + write-only + + + + + UART_CLKDIV + 0x14 + UART CLK DIV REGISTER + 32 + 0x00000000 + + + uart_clkdiv + BAUDRATE = UART_CLK_FREQ / UART_CLKDIV + 0 + 20 + read-write + + + + + UART_AUTOBAUD + 0x18 + UART BAUDRATE DETECT REGISTER + 32 + 0x00000000 + + + glitch_filt + 8 + 8 + read-write + + + autobaud_en + Set this bit to enable baudrate detect + 0 + 1 + read-write + + + + + UART_STATUS + 0x1c + UART STATUS REGISTER + 32 + 0x00000000 + + + txd + The level of the uart txd pin + 31 + 1 + read-only + + + rtsn + The level of uart rts pin + 30 + 1 + read-only + + + dtrn + The level of uart dtr pin + 29 + 1 + read-only + + + txfifo_cnt + Number of data in UART TX fifo + 16 + 8 + read-only + + + rxd + The level of uart rxd pin + 15 + 1 + read-only + + + ctsn + The level of uart cts pin + 14 + 1 + read-only + + + dsrn + The level of uart dsr pin + 13 + 1 + read-only + + + rxfifo_cnt + Number of data in uart rx fifo + 0 + 8 + read-only + + + + + UART_CONF0 + 0x20 + UART CONFIG0(UART0 and UART1) + 32 + 0x00000000 + + + uart_dtr_inv + Set this bit to inverse uart dtr level + 24 + 1 + read-write + + + uart_rts_inv + Set this bit to inverse uart rts level + 23 + 1 + read-write + + + uart_txd_inv + Set this bit to inverse uart txd level + 22 + 1 + read-write + + + uart_dsr_inv + Set this bit to inverse uart dsr level + 21 + 1 + read-write + + + uart_cts_inv + Set this bit to inverse uart cts level + 20 + 1 + read-write + + + uart_rxd_inv + Set this bit to inverse uart rxd level + 19 + 1 + read-write + + + txfifo_rst + Set this bit to reset uart tx fifo + 18 + 1 + read-write + + + rxfifo_rst + Set this bit to reset uart rx fifo + 17 + 1 + read-write + + + tx_flow_en + Set this bit to enable uart tx hardware flow control + 15 + 1 + read-write + + + uart_loopback + Set this bit to enable uart loopback test mode + 14 + 1 + read-write + + + txd_brk + RESERVED, DO NOT CHANGE THIS BIT + 8 + 1 + read-write + + + sw_dtr + sw dtr + 7 + 1 + read-write + + + sw_rts + sw rts + 6 + 1 + read-write + + + stop_bit_num + Set stop bit: 1:1bit 2:1.5bits 3:2bits + 4 + 2 + read-write + + + bit_num + Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits + 2 + 2 + read-write + + + parity_en + Set this bit to enable uart parity check + 1 + 1 + read-write + + + parity + Set parity check: 0:even 1:odd, UART CONFIG1 + 0 + 1 + read-write + + + + + UART_CONF1 + 0x24 + Set this bit to enable rx time-out function + 32 + 0x00000000 + + + rx_tout_en + Set this bit to enable rx time-out function + 31 + 1 + read-write + + + rx_tout_thrhd + Config bits for rx time-out threshold,uint: byte,0-127 + 24 + 7 + read-write + + + rx_flow_en + Set this bit to enable rx hardware flow control + 23 + 1 + read-write + + + rx_flow_thrhd + The config bits for rx flow control threshold,0-127 + 16 + 7 + read-write + + + txfifo_empty_thrhd + The config bits for tx fifo empty threshold,0-127 + 8 + 7 + read-write + + + rxfifo_full_thrhd + The config bits for rx fifo full threshold,0-127 + 0 + 7 + read-write + + + + + UART_LOWPULSE + 0x28 + UART_LOWPULSE + 32 + 0x00000000 + + + lowpulse_min_cnt + used in baudrate detect + 0 + 20 + read-only + + + + + UART_HIGHPULSE + 0x2c + UART_HIGHPULSE + 32 + 0x00000000 + + + highpulse_min_cnt + used in baudrate detect + 0 + 20 + read-only + + + + + UART_RXD_CNT + 0x30 + UART_RXD_CNT + 32 + 0x00000000 + + + rxd_edge_cnt + used in baudrate detect + 0 + 10 + read-only + + + + + UART_DATE + 0x78 + UART HW INFO + 32 + 0x00000000 + + + uart_date + UART HW INFO + 0 + 32 + read-write + + + + + UART_ID + 0x7c + UART_ID + 32 + 0x00000000 + + + uart_id + 0 + 32 + read-write + + + + + + + WDT + 0x60000900 + + 0 + 0x00000080 + registers + + + + WDT_CTL + 0x0 + WDT_CTL + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + WDT_OP + 0x4 + WDT_OP + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + WDT_OP_ND + 0x8 + WDT_OP_ND + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + WDT_RST + 0x14 + WDT_RST + 32 + 0x00000000 + + + Register + 0 + 32 + read-write + + + + + + RNGRNG register0x3FF20E44032RNG registerrngRNG register032read-only0 + + WATCHDOGWatchdog registers0x60000900024Watchdog registersctlenableEnable the watchdog timer.01 + stage_1_no_resetWhen set to 1, and running in two-stage mode, it turns the watchdog into a single shot timer that doesn't reset the device.11 + stage_1_disableSet to 1 to disable the stage 1 of the watchdog timer21 + unknown_331 + unknown_441 + unknown_551 + Watchdog control032read-write0 + reload_stage0Reload value for stage 0432read-write0 + reload_stage1Reload value for stage 1832read-write0 + countWatchdog clock cycle count1232read-write0 + stageThe current watchdog stage1632read-write0 + resetWatchdog reset2032read-write0 + reset_stageWatchdog stage reset2432read-write0 + + + \ No newline at end of file