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Basic floating-point components for RISC-V processors
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SCR fix some bugs. Optimize timing. Add new tests for f64 Mar 9, 2019
doc initial document Aug 13, 2017
patching_testfloat
rtl fix bugs in testbench Mar 9, 2019
tb fix bugs in testbench Mar 9, 2019
tb_dw fix bugs on exception flags Aug 21, 2018
README.md README updated Aug 13, 2017

README.md

RISCV-FPU

This project is aiming to design necessary floating-piont components for implementing RISCV processors.

These components need to be tweaked for different implementations. I provide them just as reference designs. They have better PPA than the Berkeley hard-float and synopsys DesignWare.

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