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Comment on the rocket-chip source code
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xidian95liu fix iPorts oPorts
iports的类型为Seq[(Int, OutwardNode [DI, UI, BI])],oParams对iports进行操作的mapParamsDl类型(Int,Seq[DI])=>Seq[DO]
oports的类型则为Seq[(Int, InwardNode [DO, UO, BO])]
Latest commit 7701f1d Oct 19, 2018
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amba/apb finish refactor accordingly Jul 9, 2017
chip change license to CC BY-NC-SA 4.0 Jul 31, 2017
coreplex add RTC Aug 16, 2017
devices add plic to index Sep 26, 2017
diplomacy fix iPorts oPorts Oct 19, 2018
other move bus from tile to tilelink in index Sep 26, 2017
regmapper finish PLIC Sep 26, 2017
rocket change license to CC BY-NC-SA 4.0 Jul 31, 2017
tile finish rocket tile Aug 8, 2017
tilelink clean up tilelink/Parameter syntax and add it into index Sep 25, 2017
util add util.generatorutils Aug 8, 2017
.gitignore begin to understand the Node defs Mar 5, 2017 place holder for basecoreplex Aug 8, 2017 change license to CC BY-NC-SA 4.0 Jul 31, 2017 add RTC Aug 16, 2017 placeholder for Plic Aug 24, 2017 place holder for basecoreplex Aug 8, 2017 working on the RegMapper Sep 21, 2017 change license to CC BY-NC-SA 4.0 Jul 31, 2017 finish RegisterRouter Sep 25, 2017 add util.generatorutils Aug 8, 2017

Notes for Rocket-Chip

  • amba This RTL package uses diplomacy to generate bus implementations of AMBA protocols, including AXI4, AHB-lite, and APB.
  • chip This top-level utility package invokes Chisel to elaborate a particular configuration of a coreplex, along with the appropriate testing collateral.
  • config This utility package provides Scala interfaces for configuring a generator via a dynamically-scoped parameterization library.
  • coreplex This RTL package generates a complete coreplex by gluing together a variety of components from other packages, including: tiled Rocket cores, a system bus network, coherence agents, debug devices, interrupt handlers, externally-facing peripherals, clock-crossers and converters from TileLink to external bus protocols (e.g. AXI or AHB).
  • devices This RTL package contains implementations for peripheral devices, including the Debug module and various TL slaves.
  • diplomacy This utility package extends Chisel by allowing for two-phase hardware elaboration, in which certain parameters are dynamically negotiated between modules.
  • groundtest This RTL package generates synthesizeable hardware testers that emit randomized memory access streams in order to stress-tests the uncore memory hierarchy.
  • jtag This RTL package provides definitions for generating JTAG bus interfaces.
  • regmapper This utility package generates slave devices with a standardized interface for accessing their memory-mapped registers.
  • rocket This RTL package generates the Rocket in-order pipelined core, as well as the L1 instruction and data caches. This library is intended to be used by a chip generator that instantiates the core within a memory system and connects it to the outside world.
  • tile This RTL package contains components that can be combined with cores to construct tiles, such as FPUs and accelerators.
  • tilelink This RTL package uses diplomacy to generate bus implementations of the TileLink protocol. It also contains a variety of adapters and protocol converters.
  • unittest This utility package contains a framework for generateing synthesizeable hardware testers of individual modules.
  • util This utility package provides a variety of common Scala and Chisel constructs that are re-used across multiple other packages.

The document is partially based on commit #aff028f8 07 Aug. 2017.

Last updated: 08/08/2017
CC BY-NC-SA 4.0, © (2017) Wei Song
Apache 2.0, © (2016-2017) SiFive, Inc
BSD, © (2012-2014, 2016) The Regents of the University of California (Regents)

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