Update RISC-V ISA documentation

content/languages/riscv/index.md

@@ -10,9 +10,29 @@ Beta
 
 ## Version
 
-RV64
-
-Codewars uses [QEMU user mode emulation](https://www.qemu.org/docs/master/user/main.html) to support RISC-V content. The [RISC-V `virt` board in QEMU full system emulation](https://www.qemu.org/docs/master/system/riscv/virt.html) implements **RV64IMAFDC**, also known as **RV64GC**. This is likely the case for user mode emulation as well but is not officially documented at the time of writing (2022-08-21).
+QEMU Toolchain: QEMU 7.1, GCC 11.3.0, Binutils 2.38
+
+ISA String: RV64GCV_Zba_Zbb_Zbc_Zbs_Zbkx_Zk_Zks
+
+Codewars uses [QEMU user mode emulation](https://www.qemu.org/docs/master/user/main.html) to support RISC-V content. Codewars is configured to use the following extensions for RISC-V:
+- `G` - General-Purpose<sup>*</sup>
+- `C` - Compressed<sup>*</sup>
+- `V` - Vector<sup>*†</sup>
+- Zb* - Bit-Manipulation<sup>‡</sup>
+    - `Zba` - Address Generation
+    - `Zbb` - Basic
+    - `Zbc` - Carry-less
+    - `Zbs` - Single-bit
+- Cryptography - Scalar<sup>§</sup>
+    - `Zbkx` - Crossbar permutation
+    - `Zk` - Standard
+    - `Zks` - ShangMi
+
+The most recent version of the specification for each can be downloaded below (as of 26 Dec 2023):
+- <sup>*</sup><a href="https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-056b6ff-2023-10-02/unpriv-isa-asciidoc.pdf">RISC-V Unprivileged Specification</a>
+- <sup>†</sup><a href="https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf">Vector Extension Specification</a>
+- <sup>‡</sup><a href="https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf">Bit-Manipulation Extension Specification</a>
+- <sup>§</sup><a href="https://github.com/riscv/riscv-crypto/releases/download/v1.0.1-scalar/riscv-crypto-spec-scalar-v1.0.1.pdf">Cryptography Extension Specification</a>
 
 ## Test Frameworks