Skip to content
master
Switch branches/tags
Code
This branch is up to date with master.
Contribute

Latest commit

 

Git stats

Files

Permalink
Failed to load latest commit information.
Type
Name
Latest commit message
Commit time
 
 
 
 

Protoip (IP prototyping in FPGA hardware)

Protoip is a utility for quickly prototyping C-based IP in FPGA hardware: abstracting many specific low level FPGA design details, protoip shifts main focus to IP (algorithm) coding (C/C++ programming language), and boosts productivity.

Protoip provides Tcl-based functions accessible by both Xilinx Vivado Design Suite and Matlab, custom templates, examples and tutorials to support all design phases.

Protoip is a Xilinx TclStore application and comes together with Xilinx Vivado Design Suite.

Documentation

The wiki contains documentation on how to use Protoip from both Xilinx Vivado and Matlab software. Example designs are also available.

How to cite

@INPROCEEDINGS{protoip, 
author={B. Khusainov and E. C. Kerrigan and A. Suardi and  G. A. Constantinides}, 
booktitle={IFAC World Congress 2017}, 
title={Nonlinear predictive control on a heterogeneous computing platform}, 
year={2017}, 
month={July},}

This work has been supported by the EPSRC Impact Acceleration grant number EP/K503733/1

About

IP prototyping in FPGA hardware

Resources

Releases

No releases published

Packages

No packages published