Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
mb/asrock: Add ASRock H77 Pro4-M mainboard
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM. The port was initially done with autoport. It is quite similar to the ASRock B75 Pro3-M which is already supported by coreboot. Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 combined port (mouse or keyboard) - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - All rear and internal USB3 ports with reasonable transfer rates - All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) - All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) - Rear eSATA connector (multiplexed with one ASM1061 port) - Console output on the serial port of the Super I/O - SeaBIOS 1.15.0 to boot slackware64 - SeaBIOS 1.15.0 to boot Windows 10 (needs VGA BIOS) - Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`) - External flashing with flashrom-1.2 and a Raspberry Pi 1 - S3 suspend/resume from either Linux or Windows 10 Not working: - Booting from the two SATA ports provided by the ASM1061 - Automatic fan control with the NCT6776D Super I/O Untested: - VBT (it is included, though) - Infrared header Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- Loading branch information
Showing
18 changed files
with
826 additions
and
0 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,174 @@ | ||
# ASRock H77 Pro4-M | ||
|
||
The ASRock H77 Pro4-M is a microATX-sized desktop board for Intel Sandy | ||
Bridge and Ivy Bridge CPUs. | ||
|
||
## Technology | ||
|
||
```eval_rst | ||
+------------------+--------------------------------------------------+ | ||
| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | | ||
+------------------+--------------------------------------------------+ | ||
| Southbridge | Intel H77 (bd82x6x) | | ||
+------------------+--------------------------------------------------+ | ||
| CPU socket | LGA 1155 | | ||
+------------------+--------------------------------------------------+ | ||
| RAM | 4 x DDR3-1600 | | ||
+------------------+--------------------------------------------------+ | ||
| Super I/O | Nuvoton NCT6776 | | ||
+------------------+--------------------------------------------------+ | ||
| Audio | Realtek ALC892 | | ||
+------------------+--------------------------------------------------+ | ||
| Network | Realtek RTL8111E | | ||
+------------------+--------------------------------------------------+ | ||
| Serial | Internal header (RS-232) | | ||
+------------------+--------------------------------------------------+ | ||
``` | ||
|
||
## Status | ||
|
||
Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12 | ||
(linux-4.19.50). | ||
|
||
### Working | ||
|
||
- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) | ||
- Native RAM initialization with four DIMMs | ||
- PS/2 combined port (mouse or keyboard) | ||
- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) | ||
- PCIe graphics in the PEG slot | ||
- All three additional PCIe slots | ||
- All rear and internal USB2 ports | ||
- All rear and internal USB3 ports | ||
- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) | ||
- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) | ||
- Rear eSATA connector (multiplexed with one ASM1061 port) | ||
- Gigabit Ethernet | ||
- Console output on the serial port | ||
- SeaBIOS 1.14.0 and 1.15.0 to boot Windows 10 (needs VGA BIOS) and Linux via | ||
extlinux | ||
- Internal flashing with flashrom-1.2, see | ||
[Internal Programming](#internal-programming) | ||
- External flashing with flashrom-1.2 and a Raspberry Pi 1 | ||
- S3 suspend/resume from either Linux or Windows 10 | ||
- Poweroff | ||
|
||
### Not working | ||
|
||
- Booting from the two SATA ports provided by the ASM1061 | ||
- Automatic fan control with the NCT6776D Super I/O | ||
|
||
### Untested | ||
|
||
- EHCI debug | ||
- S/PDIF audio | ||
- Other audio jacks than the green one, and the front panel header | ||
- Parallel port | ||
- Infrared/CIR | ||
- Wakeup from anything but the power button | ||
|
||
## Flashing coreboot | ||
|
||
```eval_rst | ||
+---------------------+------------+ | ||
| Type | Value | | ||
+=====================+============+ | ||
| Socketed flash | yes | | ||
+---------------------+------------+ | ||
| Model | W25Q64.V | | ||
+---------------------+------------+ | ||
| Size | 8 MiB | | ||
+---------------------+------------+ | ||
| Package | DIP-8 | | ||
+---------------------+------------+ | ||
| Write protection | no | | ||
+---------------------+------------+ | ||
| Dual BIOS feature | no | | ||
+---------------------+------------+ | ||
| Internal flashing | yes | | ||
+---------------------+------------+ | ||
``` | ||
|
||
The flash is divided into the following regions, as obtained with | ||
`ifdtool -f rom.layout backup.rom`: | ||
``` | ||
00000000:00000fff fd | ||
00200000:007fffff bios | ||
00001000:001fffff me | ||
``` | ||
|
||
### Internal programming | ||
|
||
The main SPI flash can be accessed using flashrom. By default, only | ||
the BIOS region of the flash is writable. If you wish to change any | ||
other region (Management Engine or flash descriptor), then an external | ||
programmer is required. | ||
|
||
The following command may be used to flash coreboot: | ||
|
||
``` | ||
$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom | ||
``` | ||
|
||
The use of `--noverify-all` is required since the Management Engine | ||
region is not readable even by the host. | ||
|
||
```eval_rst | ||
In addition to the information here, please see the | ||
:doc:`../../flash_tutorial/index`. | ||
``` | ||
|
||
## Hardware monitoring and fan control | ||
|
||
There are two fan headers for the CPU cooler, CPU_FAN1 and CPU_FAN2. They share | ||
a single fan tachometer input on the Super I/O while some dedicated logic | ||
selects which one is allowed to reach it. Two GPIO pins on the Super I/O are | ||
used to control that logic. The firmware has to set them; coreboot selects | ||
CPU_FAN1 by default, but the user can change that setting if it was built with | ||
CONFIG_USE_OPTION_TABLE: | ||
|
||
``` | ||
$ sudo nvramtool -e cpu_fan_header | ||
[..] | ||
$ sudo nvramtool -w cpu_fan_header=CPU_FAN2 | ||
$ sudo nvramtool -w cpu_fan_header=None | ||
$ sudo nvramtool -w cpu_fan_header=Both | ||
``` | ||
|
||
The setting will take effect after a reboot. Selecting and connecting both fan | ||
headers is possible but the Super I/O will report wrong fan speeds. | ||
|
||
Currently there is no automatic, OS-independent fan control, but a software | ||
like `fancontrol` from the lm-sensors package can be used instead. | ||
|
||
## Serial port header | ||
|
||
Serial port 1, provided by the Super I/O, is exposed on a pin header. The | ||
RS-232 signals are assigned to the header so that its pin numbers map directly | ||
to the pin numbers of a DE-9 connector. If your serial port doesn't seem to | ||
work, check if your bracket expects a different assignment. Also don't try to | ||
connect it directly to a device that operates at TTL levels - it would need a | ||
level converter like a MAX232. | ||
|
||
Here is a top view of the serial port header found on this board: | ||
|
||
+---+---+ | ||
N/C | | 9 | RI -> pin 9 | ||
+---+---+ | ||
Pin 8 <- CTS | 8 | 7 | RTS -> pin 7 | ||
+---+---+ | ||
Pin 6 <- DSR | 6 | 5 | GND -> pin 5 | ||
+---+---+ | ||
Pin 4 <- DTR | 4 | 3 | TxD -> pin 3 | ||
+---+---+ | ||
Pin 2 <- RxD | 2 | 1 | DCD -> pin 1 | ||
+---+---+ | ||
|
||
## eSATA | ||
|
||
The eSATA port on the rear I/O panel and the internal connector SATA3_A1 share | ||
the same controller port on the ASM1061. Attaching an eSATA drive causes a | ||
multiplexer chip to disconnect the internal port from the SATA controller and | ||
connect the eSATA port instead. This can be seen on GP23 of the Super I/O | ||
GPIOs: it is '0' when something is connected to the eSATA port and '1' | ||
otherwise. |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,27 @@ | ||
# SPDX-License-Identifier: GPL-2.0-or-later | ||
|
||
if BOARD_ASROCK_H77PRO4_M | ||
|
||
config BOARD_SPECIFIC_OPTIONS | ||
def_bool y | ||
select BOARD_ROMSIZE_KB_8192 | ||
select DRIVERS_ASMEDIA_ASPM_BLACKLIST | ||
select HAVE_ACPI_RESUME | ||
select HAVE_ACPI_TABLES | ||
select HAVE_CMOS_DEFAULT | ||
select HAVE_OPTION_TABLE | ||
select INTEL_GMA_HAVE_VBT | ||
select MAINBOARD_HAS_LIBGFXINIT | ||
select NORTHBRIDGE_INTEL_SANDYBRIDGE | ||
select SERIRQ_CONTINUOUS_MODE | ||
select SOUTHBRIDGE_INTEL_C216 | ||
select SUPERIO_NUVOTON_NCT6776 | ||
select USE_NATIVE_RAMINIT | ||
|
||
config MAINBOARD_DIR | ||
default "asrock/h77pro4-m" | ||
|
||
config MAINBOARD_PART_NUMBER | ||
default "H77 Pro4-M" | ||
|
||
endif |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,2 @@ | ||
config BOARD_ASROCK_H77PRO4_M | ||
bool "H77 Pro4-M" |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,7 @@ | ||
# SPDX-License-Identifier: GPL-2.0-only | ||
|
||
bootblock-y += early_init.c | ||
bootblock-y += gpio.c | ||
romstage-y += early_init.c | ||
romstage-y += gpio.c | ||
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads |
Empty file.
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,10 @@ | ||
/* SPDX-License-Identifier: GPL-2.0-or-later */ | ||
|
||
Method(_WAK, 1) | ||
{ | ||
Return(Package() {0, 0}) | ||
} | ||
|
||
Method(_PTS, 1) | ||
{ | ||
} |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,3 @@ | ||
/* SPDX-License-Identifier: GPL-2.0-only */ | ||
|
||
#include <drivers/pc80/pc/ps2_controller.asl> |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,7 @@ | ||
Category: desktop | ||
Board URL: https://www.asrock.com/mb/Intel/H77%20Pro4-M/ | ||
ROM package: DIP-8 | ||
ROM protocol: SPI | ||
ROM socketed: y | ||
Flashrom support: y | ||
Release year: 2012 |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,7 @@ | ||
boot_option=Fallback | ||
debug_level=Debug | ||
nmi=Disable | ||
power_on_after_fail=Disable | ||
sata_mode=AHCI | ||
gfx_uma_size=64M | ||
cpu_fan_tach_src=CPU_FAN1 |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,96 @@ | ||
## SPDX-License-Identifier: GPL-2.0-only | ||
|
||
# ----------------------------------------------------------------- | ||
entries | ||
|
||
# ----------------------------------------------------------------- | ||
0 120 r 0 reserved_memory | ||
|
||
# ----------------------------------------------------------------- | ||
# RTC_BOOT_BYTE (coreboot hardcoded) | ||
384 1 e 2 boot_option | ||
388 4 h 0 reboot_counter | ||
|
||
# ----------------------------------------------------------------- | ||
# coreboot config options: console | ||
395 4 e 3 debug_level | ||
|
||
# coreboot config options: southbridge | ||
408 1 e 1 nmi | ||
|
||
409 2 e 4 power_on_after_fail | ||
411 2 e 5 sata_mode | ||
|
||
# coreboot config options: northbridge | ||
416 5 e 6 gfx_uma_size | ||
|
||
# coreboot config options: mainboard-specific | ||
421 2 e 7 cpu_fan_tach_src | ||
|
||
# coreboot config options: check sums | ||
984 16 h 0 check_sum | ||
|
||
# ----------------------------------------------------------------- | ||
|
||
enumerations | ||
#ID value text | ||
|
||
# Generic on/off enum | ||
1 0 Disable | ||
1 1 Enable | ||
|
||
# boot_option | ||
2 0 Fallback | ||
2 1 Normal | ||
|
||
# debug_level | ||
3 0 Emergency | ||
3 1 Alert | ||
3 2 Critical | ||
3 3 Error | ||
3 4 Warning | ||
3 5 Notice | ||
3 6 Info | ||
3 7 Debug | ||
3 8 Spew | ||
|
||
# power_on_after_fail | ||
4 0 Disable | ||
4 1 Enable | ||
4 2 Keep | ||
|
||
# sata_mode | ||
5 0 AHCI | ||
5 1 Compatible | ||
5 2 Legacy | ||
|
||
# gfx_uma_size (Intel IGP Video RAM size) | ||
6 0 32M | ||
6 1 64M | ||
6 2 96M | ||
6 3 128M | ||
6 4 160M | ||
6 5 192M | ||
6 6 224M | ||
6 7 256M | ||
6 8 288M | ||
6 9 320M | ||
6 10 352M | ||
6 11 384M | ||
6 12 416M | ||
6 13 448M | ||
6 14 480M | ||
6 15 512M | ||
6 16 1024M | ||
|
||
# cpu_fan_header (select which header provides the tachometer | ||
# signal to the Super I/O on its CPUFANIN input) | ||
7 0 None | ||
7 1 CPU_FAN1 | ||
7 2 CPU_FAN2 | ||
7 3 Both | ||
|
||
# ----------------------------------------------------------------- | ||
checksums | ||
|
||
checksum 392 423 984 |
Binary file not shown.
Oops, something went wrong.