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soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake
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This is a follow-up patch to initial copy patch for Jasper Lake SoC.
Remove all Tiger Lake specfic code from Jasper Lake SoC code.

BUG=b:150217037

Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@aamirbohra @subrata-b
aamirbohra authored and subrata-b committed Mar 28, 2020
1 parent dd7acaa commit 512b77a
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Showing 66 changed files with 939 additions and 3,250 deletions.
54 changes: 16 additions & 38 deletions src/soc/intel/jasperlake/Kconfig
View file
@@ -1,22 +1,9 @@
config SOC_INTEL_TIGERLAKE_BASE_COPY
bool

config SOC_INTEL_TIGERLAKE_COPY
bool
select SOC_INTEL_TIGERLAKE_BASE_COPY
#TODO - Enable INTEL_CAR_NEM_ENHANCED
select INTEL_CAR_NEM
help
Intel Tigerlake support

config SOC_INTEL_JASPERLAKE_COPY
bool
select SOC_INTEL_TIGERLAKE_BASE_COPY
select INTEL_CAR_NEM
help
Intel Jasperlake support

if SOC_INTEL_TIGERLAKE_BASE_COPY
if SOC_INTEL_JASPERLAKE_COPY

config CPU_SPECIFIC_OPTIONS
def_bool y
Expand All @@ -36,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC
Expand Down Expand Up @@ -84,13 +72,12 @@ config DCACHE_RAM_SIZE

config DCACHE_BSP_STACK_SIZE
hex
default 0x40400 if SOC_INTEL_TIGERLAKE_COPY
default 0x30400 if SOC_INTEL_JASPERLAKE_COPY
default 0x30400
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value will be
sum of FSP-M stack requirement (256KiB for TGL, 192KiB for JSL) and CB romstage
stack requirement (~1KiB).
other stages. In the case of FSP_USES_CB_STACK default value
will be sum of FSP-M stack requirement(192 KiB) and CB romstage
stack requirement(~1KiB).

config FSP_TEMP_RAM_SIZE
hex
Expand All @@ -102,8 +89,7 @@ config FSP_TEMP_RAM_SIZE

config IFD_CHIPSET
string
default "jsl" if SOC_INTEL_JASPERLAKE_COPY
default "tgl" if SOC_INTEL_TIGERLAKE_COPY
default "jsl"

config IED_REGION_SIZE
hex
Expand All @@ -115,13 +101,11 @@ config HEAP_SIZE

config MAX_ROOT_PORTS
int
default 8 if SOC_INTEL_JASPERLAKE_COPY
default 12 if SOC_INTEL_TIGERLAKE_COPY
default 8

config MAX_PCIE_CLOCKS
int
default 7 if SOC_INTEL_TIGERLAKE_COPY
default 6 if SOC_INTEL_JASPERLAKE_COPY
default 6

config SMM_TSEG_SIZE
hex
Expand Down Expand Up @@ -155,8 +139,7 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ

config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
default 3 if SOC_INTEL_JASPERLAKE_COPY
default 4 if SOC_INTEL_TIGERLAKE_COPY
default 3

config SOC_INTEL_I2C_DEV_MAX
int
Expand All @@ -173,17 +156,14 @@ config CONSOLE_UART_BASE_ADDRESS

# Clock divider parameters for 115200 baud rate
# Baudrate = (UART source clcok * M) /(N *16)
# TGL UART source clock: 120MHz
# JSL UART source clock: 100MHz
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex
default 0x30 if SOC_INTEL_JASPERLAKE_COPY
default 0x25a if SOC_INTEL_TIGERLAKE_COPY
default 0x30

config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0xc35 if SOC_INTEL_JASPERLAKE_COPY
default 0x7fff if SOC_INTEL_TIGERLAKE_COPY
default 0xc35

config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
Expand All @@ -205,17 +185,15 @@ config CBFS_SIZE

config FSP_HEADER_PATH
string "Location of FSP headers"
default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" if SOC_INTEL_JASPERLAKE_COPY
default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" if SOC_INTEL_TIGERLAKE_COPY
default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/"

config FSP_FD_PATH
string
depends on FSP_USE_REPO
default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE_COPY
default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE_COPY
default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd"

config SOC_INTEL_TIGERLAKE_COPY_DEBUG_CONSENT
int "Debug Consent for TGL"
config SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT
int "Debug Consent for JSL"
# USB DBC is more common for developers so make this default to 3 if
# SOC_INTEL_DEBUG_CONSENT=y
default 3 if SOC_INTEL_DEBUG_CONSENT
Expand Down
26 changes: 10 additions & 16 deletions src/soc/intel/jasperlake/Makefile.inc
View file
@@ -1,4 +1,4 @@
ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE_COPY),y)
ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE_COPY),y)

subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode
Expand All @@ -20,15 +20,12 @@ bootblock-y += bootblock/cpu.c
bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c
bootblock-y += espi.c
bootblock-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
bootblock-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c
bootblock-y += gpio.c
bootblock-y += p2sb.c

romstage-y += espi.c
romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += meminit_tgl.c
romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += meminit_jsl.c
romstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
romstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c
romstage-y += gpio.c
romstage-y += meminit.c
romstage-y += reset.c

ramstage-y += acpi.c
Expand All @@ -37,10 +34,8 @@ ramstage-y += cpu.c
ramstage-y += elog.c
ramstage-y += espi.c
ramstage-y += finalize.c
ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += fsp_params_tgl.c
ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += fsp_params_jsl.c
ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c
ramstage-y += fsp_params.c
ramstage-y += gpio.c
ramstage-y += graphics.c
ramstage-y += lockdown.c
ramstage-y += p2sb.c
Expand All @@ -50,17 +45,16 @@ ramstage-y += smmrelocate.c
ramstage-y += systemagent.c
ramstage-y += sd.c

smm-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
smm-$(CONFIG_SOC_INTEL_JASPERLAKE_COPY) += gpio_jsl.c
smm-y += gpio.c
smm-y += p2sb.c
smm-y += pmc.c
smm-y += pmutil.c
smm-y += smihandler.c
smm-y += uart.c

verstage-$(CONFIG_SOC_INTEL_TIGERLAKE_COPY) += gpio_tgl.c
verstage-y += gpio.c

CPPFLAGS_common += -I$(src)/soc/intel/tigerlake
CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include
CPPFLAGS_common += -I$(src)/soc/intel/jasperlake
CPPFLAGS_common += -I$(src)/soc/intel/jasperlake/include

endif
131 changes: 126 additions & 5 deletions src/soc/intel/jasperlake/acpi/pci_irqs.asl
View file
Expand Up @@ -13,8 +13,129 @@
* GNU General Public License for more details.
*/

#if CONFIG(SOC_INTEL_TIGERLAKE_COPY)
#include "pci_irqs_tgl.asl"
#else
#include "pci_irqs_jsl.asl"
#endif
#include <soc/irq.h>

Name (PICP, Package () {
/* cAVS, SMBus, GbE, Northpeak */
Package(){0x001FFFFF, 3, 0, cAVS_INTA_IRQ },
Package(){0x001FFFFF, 4, 0, SMBUS_INTB_IRQ },
Package(){0x001FFFFF, 6, 0, GbE_INTC_IRQ },
Package(){0x001FFFFF, 7, 0, TRACE_HUB_INTD_IRQ },
/* SerialIo */
Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
/* PCI Express Port 1-8 */
Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
/* eMMC */
Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
/* SerialIo */
Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
/* SATA controller */
Package(){0x0017FFFF, 0, 0, SATA_IRQ },
/* CSME (HECI, IDE-R, Keyboard and Text redirection */
Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
Package(){0x0016FFFF, 2, 0, IDER_IRQ },
Package(){0x0016FFFF, 3, 0, KT_IRQ },
Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
/* SerialIo */
Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
Package(){0x0014FFFF, 1, 0, OTG_IRQ },
Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
Package(){0x0014FFFF, 5, 0, SD_IRQ },
/* SerialIo */
Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
/* SA IGFX Device */
Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
/* SA Thermal Device */
Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
/* SA IPU Device */
Package(){0x0005FFFF, 0, 0, IPU_IRQ },
/* SA GNA Device */
Package(){0x0008FFFF, 0, 0, GNA_IRQ },
})

Name (PICN, Package () {
/* D31: cAVS, SMBus, GbE, Northpeak */
Package () { 0x001FFFFF, 3, 0, 11 },
Package () { 0x001FFFFF, 4, 0, 10 },
Package () { 0x001FFFFF, 6, 0, 11 },
Package () { 0x001FFFFF, 7, 0, 11 },
/* D30: SerialIo */
Package () {0x001EFFFF, 0, 0, 11 },
Package () {0x001EFFFF, 1, 0, 10 },
Package () {0x001EFFFF, 2, 0, 11 },
Package () {0x001EFFFF, 3, 0, 11 },
/* D28: PCI Express Port 1-8 */
Package () { 0x001CFFFF, 0, 0, 11 },
Package () { 0x001CFFFF, 1, 0, 10 },
Package () { 0x001CFFFF, 2, 0, 11 },
Package () { 0x001CFFFF, 3, 0, 11 },
Package () { 0x001CFFFF, 4, 0, 11 },
Package () { 0x001CFFFF, 5, 0, 10 },
Package () { 0x001CFFFF, 6, 0, 11 },
Package () { 0x001CFFFF, 7, 0, 11 },
/* D26: eMMC */
Package(){0x001AFFFF, 0, 0, 11 },
/* D25: SerialIo */
Package () {0x0019FFFF, 0, 0, 11 },
Package () {0x0019FFFF, 1, 0, 10 },
Package () {0x0019FFFF, 2, 0, 11 },
/* D23: SATA controller */
Package () { 0x0017FFFF, 0, 0, 11 },
/* D22: CSME (HECI, IDE-R, KT redirection */
Package () { 0x0016FFFF, 0, 0, 11 },
Package () { 0x0016FFFF, 1, 0, 10 },
Package () { 0x0016FFFF, 2, 0, 11 },
Package () { 0x0016FFFF, 3, 0, 11 },
Package () { 0x0016FFFF, 4, 0, 11 },
Package () { 0x0016FFFF, 5, 0, 11 },
/* D21: SerialIo */
Package () {0x0015FFFF, 0, 0, 11 },
Package () {0x0015FFFF, 1, 0, 10 },
Package () {0x0015FFFF, 2, 0, 11 },
Package () {0x0015FFFF, 3, 0, 11 },
/* D20: xHCI, OTG, SRAM, CNVi WiFi, SD */
Package () { 0x0014FFFF, 0, 0, 11 },
Package () { 0x0014FFFF, 1, 0, 10 },
Package () { 0x0014FFFF, 2, 0, 11 },
Package () { 0x0014FFFF, 3, 0, 11 },
Package () { 0x0014FFFF, 5, 0, 11 },
/* D18: SerialIo */
Package () {0x0012FFFF, 6, 0, 11 },
/* SA IGFX Device */
Package () {0x0002FFFF, 0, 0, 11 },
/* SA Thermal Device */
Package () { 0x0004FFFF, 0, 0, 11 },
/* SA IPU Device */
Package () { 0x0005FFFF, 0, 0, 11 },
/* SA GNA Device */
Package () { 0x0008FFFF, 0, 0, 11 },
})

Method (_PRT)
{
If (PICM) {
Return (^PICP)
} Else {
Return (^PICN)
}
}

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