diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb
index 0dc77f3ea3e..2913519ca98 100644
--- a/src/mainboard/asus/p8x7x-series/devicetree.cb
+++ b/src/mainboard/asus/p8x7x-series/devicetree.cb
@@ -1,6 +1,24 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 chip northbridge/intel/sandybridge
+	# All MRC-capable boards in family (P8Z77-M[ PRO]) lists supported
+	# DIMMs down to 1.25v
+	register "ddr3lv_support" = "1"
+	# FIXME: Nothing can run native at 800MHz on p8z77-m, others may have same problem
+	register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
+
+	register "usb_port_config" = "{
+		{1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
+		{1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
+		{1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080}
+		}"
+	# 4 bit switch mask. 0=not switchable, 1=switchable
+	# Means once it's loaded the OS, it can swap ports
+	# from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
+	register "usb3.hs_port_switch_mask" = "0xf"
+	# (The other 3 usb3.* settings can be set from nvram options, and so are set
+	# from runtime code)
+
 	device domain 0 on
 		device ref host_bridge on  end		# Host bridge
 		device ref peg10 on  end		# PCIEX16_1
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
index 9b4fa1da498..fdb0a455a5d 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
@@ -52,34 +52,10 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 
 void mainboard_fill_pei_data(struct pei_data *pei)
 {
-	uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */
-	uint16_t usbcfg[16][3] = {
-		/* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */
-		{1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
-		{1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
-		{1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080}
-	};
+	const uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */
 
 	memcpy(pei->spd_addresses, &spdaddr, sizeof(spdaddr));
 
-	pei->gbe_enable = 0;	   /* Board uses no Intel GbE but a RTL8111F */
-	pei->max_ddr3_freq = 1600; /* 1333=Sandy; 1600=Ivy */
-
-	memcpy(pei->usb_port_config, &usbcfg, sizeof(usbcfg));
-
-	/* ASUS P8Z77-M manual lists some supported DIMMs down to 1.25v */
-	pei->ddr3lv_support = 1;
-	/*
-	 * PCIe 3.0 support. As we use Ivy Bridge, let's enable it,
-	 * but might cause some system instability!
-	 */
-	pei->pcie_init = 1;
-	/*
-	 * 4 bit switch mask. 0=not switchable, 1=switchable
-	 * Means once it's loaded the OS, it can swap ports
-	 * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
-	 */
-	pei->usb3.hs_port_switch_mask = 0xf;
 	/*
 	 * USB 3 mode settings.
 	 * These are obtained from option table then bit masked to keep within range.
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
index cad9c5c3a98..cdcaa57712a 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -1,6 +1,11 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 chip northbridge/intel/sandybridge
+	register "usb_port_config" = "{
+		{1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
+		{1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
+		{1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080}
+		}"
 	device domain 0 on
 		subsystemid 0x1043 0x84ca inherit
 		chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
index a93f5e942af..ac3eb420393 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
@@ -58,6 +58,10 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
+	const uint8_t spdaddr[] = {0xa0, 0xa2, 0xa4, 0xa6}; /* SMBus mul 2 */
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
 	/*
 	 * USB3 mode:
 	 * 0 = Disable: work always as USB 2.0(ehci)
@@ -66,88 +70,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 	 * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver
 	 *     and reboots, it will keep the USB3.0 speed
 	 */
-	unsigned int usb3_mode = get_uint_option("usb3_mode", 1);
-	usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */
-
+	pei_data->usb3.mode = get_uint_option("usb3_mode", 1) & 0x3;
 	/* Load USB3 pre-OS xHCI driver */
-	unsigned int usb3_drv = get_uint_option("usb3_drv", 1);
-	usb3_drv &= 0x1; /* ensure it's 0/1 only */
-
+	pei_data->usb3.preboot_support = get_uint_option("usb3_drv", 1) & 0x1;
 	/* Use USB3 xHCI streams */
-	unsigned int usb3_streams = get_uint_option("usb3_streams", 1);
-	usb3_streams &= 0x1; /* ensure it's 0/1 only */
-
-	struct pei_data pd = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 1, /* 0=Mobile, 1=Desktop/Server */
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */
-		.gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */
-		.max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */
-		.usb_port_config = {
-			/* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */
-			{ 1, 0, 0x0080 }, /* USB3 front internal header */
-			{ 1, 0, 0x0080 }, /* USB3 front internal header */
-			{ 1, 1, 0x0080 }, /* USB3 ETH top connector */
-			{ 1, 1, 0x0080 }, /* USB3 ETH bottom connector */
-			{ 1, 2, 0x0080 }, /* USB2 PS2 top connector */
-			{ 1, 2, 0x0080 }, /* USB2 PS2 bottom connector */
-			{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
-			{ 1, 3, 0x0080 }, /* USB2 internal header (USB78) */
-			{ 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
-			{ 1, 4, 0x0080 }, /* USB2 internal header (USB910) */
-			{ 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */
-			{ 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */
-			{ 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */
-			{ 0, 6, 0x0080 }  /* Unused. Asus DEBUG_PORT ??? */
-		},
-		.usb3 = {
-			/* 0=Disable; 1=Enable (start at USB3 speed)
-			 * 2=Auto (start as USB2 speed until OS loads)
-			 * 3=Smart Auto (like Auto but keep speed on reboot)
-			 */
-			usb3_mode,
-			/* 4 bit switch mask. 0=not switchable, 1=switchable
-			 * Means once it's loaded the OS, it can swap ports
-			 * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf
-			 */
-			0xf,
-			usb3_drv, /* 1=Load xHCI pre-OS drv */
-			/* 0=Don't use xHCI streams for better compatibility
-			 * 1=use xHCI streams for better speed
-			 */
-			usb3_streams
-		},
-		/* ASUS P8Z77-M PRO manual says 1.35v DIMMs are supported */
-		.ddr3lv_support = 1,
-		/* PCIe 3.0 support. As we use Ivy Bridge, let's enable it,
-		 * but might cause some system instability !
-		 */
-		.pcie_init = 1,
-		/* Command Rate. 0=Auto; 1=1N; 2=2N.
-		 * Leave it always at Auto for compatibility & stability
-		 */
-		.nmode = 0,
-		/* DDR refresh rate. 0=Auto based on DRAM's temperature;
-		 * 1=Normal rate for speed; 2=Double rate for stability
-		 */
-		.ddr_refresh_rate_config = 0
-	};
-
-	/* copy the data to output PEI */
-	*pei_data = pd;
+	pei_data->usb3.xhci_streams = get_uint_option("usb3_streams", 1) & 0x1;
 }
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
index 01625474310..d7aea497bfe 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
@@ -1,6 +1,11 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 chip northbridge/intel/sandybridge
+	register "usb_port_config" = "{
+		{1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
+		{1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
+		{1, 6, 0x0080}, {1, 5, 0x0080}, {0, 5, 0x0080}, {0, 6, 0x0080}
+		}"
 	device domain 0 on
 		subsystemid 0x1043 0x84ca inherit
 		chip southbridge/intel/bd82x6x
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index 5b3841a1f08..a72d9843696 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -18,7 +18,27 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x000001e8"
 	register "gpu_pch_backlight" = "0x03d00000"
 
-	register "max_mem_clock_mhz" = "666"			# DDR3-1333
+	register "ec_present" = "1"
+	# FIXME: Native raminit requires reduced max clock
+	register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
+	# Force double refresh rate
+	register "ddr_refresh_rate_config" = "DDR_REFRESH_RATE_DOUBLE"
+
+	register "usb_port_config" = "{
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 0, 4, 0x0000 },
+		{ 1, 4, 0x0080 },
+		{ 1, 4, 0x0040 },
+		{ 0, 4, 0x0000 },
+		{ 0, 4, 0x0000 },
+		{ 0, 4, 0x0000 },}"
 
 	device domain 0 on
 		device ref host_bridge on end # host bridge
diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c
index 4e9639fd945..e658d374651 100644
--- a/src/mainboard/google/butterfly/early_init.c
+++ b/src/mainboard/google/butterfly/early_init.c
@@ -74,45 +74,9 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 1,
-		.ddr3lv_support = 0,
-		.max_ddr3_freq = 1600,
-		.usb_port_config = {
-			/* enabled   USB oc pin    length */
-			{ 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */
-			{ 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */
-			{ 1, 0, 0x0040 }, /* P2: Camera (no OC) */
-			{ 0, 0, 0x0000 }, /* P3: Empty */
-			{ 0, 0, 0x0000 }, /* P4: Empty */
-			{ 0, 0, 0x0000 }, /* P5: Empty */
-			{ 0, 0, 0x0000 }, /* P6: Empty */
-			{ 0, 0, 0x0000 }, /* P7: Empty */
-			{ 0, 4, 0x0000 }, /* P8: Empty */
-			{ 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */
-			{ 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */
-			{ 0, 4, 0x0000 }, /* P11: Empty */
-			{ 0, 4, 0x0000 }, /* P12: Empty */
-			{ 0, 4, 0x0000 }, /* P13: Empty */
-		},
-		.ddr_refresh_rate_config = 2, /* Force double refresh rate */
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00};
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
 }
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index c5a0a084555..88983dcfc67 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -17,7 +17,26 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x00000200"
 	register "gpu_pch_backlight" = "0x04000000"
 
-	register "max_mem_clock_mhz" = "666"
+	register "ec_present" = "1"
+	register "ddr3lv_support" = "1"
+	# FIXME: Native raminit requires reduced max clock
+	register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
+
+	register "usb_port_config" = "{
+		{ 0, 3, 0x0000 },
+		{ 1, 0, 0x0040 },
+		{ 1, 1, 0x0040 },
+		{ 1, 3, 0x0040 },
+		{ 0, 3, 0x0000 },
+		{ 1, 3, 0x0040 },
+		{ 0, 3, 0x0000 },
+		{ 0, 3, 0x0000 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 0, 4, 0x0000 },
+		{ 0, 4, 0x0000 },
+		{ 0, 4, 0x0000 },
+		{ 0, 4, 0x0000 },}"
 
 	device domain 0 on
 		subsystemid 0x1ae0 0xc000 inherit
diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c
index 17e8b54b962..a4127f14d8f 100644
--- a/src/mainboard/google/link/early_init.c
+++ b/src/mainboard/google/link/early_init.c
@@ -83,46 +83,8 @@ static uint8_t *locate_spd(void)
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 1,
-		.ddr3lv_support = 1,
-		.max_ddr3_freq = 1600,
-		.usb_port_config = {
-			/* Empty and onboard Ports 0-7, set to un-used pin OC3 */
-			{ 0, 3, 0x0000 }, /* P0: Empty */
-			{ 1, 0, 0x0040 }, /* P1: Left USB 1  (OC0) */
-			{ 1, 1, 0x0040 }, /* P2: Left USB 2  (OC1) */
-			{ 1, 3, 0x0040 }, /* P3: SDCARD      (no OC) */
-			{ 0, 3, 0x0000 }, /* P4: Empty */
-			{ 1, 3, 0x0040 }, /* P5: WWAN        (no OC) */
-			{ 0, 3, 0x0000 }, /* P6: Empty */
-			{ 0, 3, 0x0000 }, /* P7: Empty */
-			/* Empty and onboard Ports 8-13, set to un-used pin OC4 */
-			{ 1, 4, 0x0040 }, /* P8: Camera      (no OC) */
-			{ 1, 4, 0x0040 }, /* P9: Bluetooth   (no OC) */
-			{ 0, 4, 0x0000 }, /* P10: Empty */
-			{ 0, 4, 0x0000 }, /* P11: Empty */
-			{ 0, 4, 0x0000 }, /* P12: Empty */
-			{ 0, 4, 0x0000 }, /* P13: Empty */
-		},
-	};
-	*pei_data = pei_data_template;
+	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
+
 	/* LINK has 2 channels of memory down, so spd_data[0] and [2]
 	   both need to be populated */
 	memcpy(pei_data->spd_data[0], locate_spd(),
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
index 6bc4b454d62..bf1bff36f25 100644
--- a/src/mainboard/google/parrot/devicetree.cb
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -17,7 +17,25 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x000001d4"
 	register "gpu_pch_backlight" = "0x03aa0000"
 
-	register "max_mem_clock_mhz" = "666"
+	register "ec_present" = "1"
+	# FIXME: Native raminit requires reduced max clock
+	register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
+
+	register "usb_port_config" = "{
+		{ 0, 3, 0x0000 },
+		{ 1, 0, 0x0040 },
+		{ 1, 1, 0x0040 },
+		{ 1, 1, 0x0040 },
+		{ 0, 3, 0x0000 },
+		{ 0, 3, 0x0000 },
+		{ 0, 3, 0x0000 },
+		{ 0, 3, 0x0000 },
+		{ 1, 4, 0x0040 },
+		{ 0, 4, 0x0000 },
+		{ 1, 4, 0x0040 },
+		{ 0, 4, 0x0000 },
+		{ 0, 4, 0x0000 },
+		{ 0, 4, 0x0000 },}"
 
 	device domain 0 on
 		device ref host_bridge on end # host bridge
diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c
index ba93531cb5b..efdb9a2fead 100644
--- a/src/mainboard/google/parrot/early_init.c
+++ b/src/mainboard/google/parrot/early_init.c
@@ -52,46 +52,11 @@ void mainboard_late_rcba_config(void)
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 1,
-		.max_ddr3_freq = 1600,
-		.usb_port_config = {
-			/* Empty and onboard Ports 0-7, set to un-used pin OC3 */
-			{ 0, 3, 0x0000 }, /* P0: Empty */
-			{ 1, 0, 0x0040 }, /* P1: Left USB 1  (OC0) */
-			{ 1, 1, 0x0040 }, /* P2: Left USB 2  (OC1) */
-			{ 1, 1, 0x0040 }, /* P3: Left USB 3  (OC1) */
-			{ 0, 3, 0x0000 }, /* P4: Empty */
-			{ 0, 3, 0x0000 }, /* P5: Empty */
-			{ 0, 3, 0x0000 }, /* P6: Empty */
-			{ 0, 3, 0x0000 }, /* P7: Empty */
-			/* Empty and onboard Ports 8-13, set to un-used pin OC4 */
-			{ 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */
-			{ 0, 4, 0x0000 }, /* P9: Empty */
-			{ 1, 4, 0x0040 }, /* P10: Camera (no OC) */
-			{ 0, 4, 0x0000 }, /* P11: Empty */
-			{ 0, 4, 0x0000 }, /* P12: Empty */
-			{ 0, 4, 0x0000 }, /* P13: Empty */
-		},
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00};
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 6710b41ac62..a2b8452d995 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -17,7 +17,30 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x06100610"
 
-	register "max_mem_clock_mhz" = "666"
+	register "ec_present" = "1"
+	# FIXME: Native raminit requires reduced max clock
+	register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800"
+
+	register "usb_port_config" = "{
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 0, 1, 0x0000 },
+		{ 1, 1, 0x0040 },
+		{ 1, 1, 0x0040 },
+		{ 1, 1, 0x0040 },
+		{ 0, 1, 0x0000 },
+		{ 0, 1, 0x0000 },
+		{ 0, 5, 0x0000 },
+		{ 1, 4, 0x0040 },
+		{ 0, 5, 0x0000 },
+		{ 0, 5, 0x0000 },
+		{ 0, 5, 0x0000 },
+		{ 1, 5, 0x0040 },}"
+
+	register "usb3.mode" = "2" # Auto
+	register "usb3.hs_port_switch_mask" = "3" # Ports 0 & 1
+	register "usb3.preboot_support" = "0" # No PreOS boot support
+	register "usb3.xhci_streams" = "1" # Sure, lets have streams
 
 	chip cpu/intel/model_206ax
 		device cpu_cluster 0 on end
diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c
index e5ed8e91ac1..85c4e154dd6 100644
--- a/src/mainboard/google/stout/early_init.c
+++ b/src/mainboard/google/stout/early_init.c
@@ -89,51 +89,11 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 1,
-		.max_ddr3_freq = 1600,
-		.usb_port_config = {
-			/* enabled   USB oc pin    length */
-			{ 1, 0, 0x0040 }, /* P0: USB 3.0 1  (OC0) */
-			{ 1, 0, 0x0040 }, /* P1: USB 3.0 2  (OC0) */
-			{ 0, 1, 0x0000 }, /* P2: Empty */
-			{ 1, 1, 0x0040 }, /* P3: Camera (no OC) */
-			{ 1, 1, 0x0040 }, /* P4: WLAN   (no OC) */
-			{ 1, 1, 0x0040 }, /* P5: WWAN   (no OC) */
-			{ 0, 1, 0x0000 }, /* P6: Empty */
-			{ 0, 1, 0x0000 }, /* P7: Empty */
-			{ 0, 5, 0x0000 }, /* P8: Empty */
-			{ 1, 4, 0x0040 }, /* P9: USB 2.0 (AUO4) (OC4) */
-			{ 0, 5, 0x0000 }, /* P10: Empty */
-			{ 0, 5, 0x0000 }, /* P11: Empty */
-			{ 0, 5, 0x0000 }, /* P12: Empty */
-			{ 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */
-		},
-		.usb3 = {
-			.mode = XHCI_MODE,
-			.hs_port_switch_mask = XHCI_PORTS,
-			.preboot_support = XHCI_PREBOOT,
-			.xhci_streams = XHCI_STREAMS,
-		},
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00};
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
 }
 
 void mainboard_early_init(int s3resume)
diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb
index 885043649cd..37304f21677 100644
--- a/src/mainboard/intel/dcp847ske/devicetree.cb
+++ b/src/mainboard/intel/dcp847ske/devicetree.cb
@@ -11,6 +11,25 @@ chip northbridge/intel/sandybridge
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
+	# 1333MHz RAM frequency
+	register "max_mem_clock_mhz" = "666"
+
+	register "usb_port_config" = "{
+		{1, 0, 0x0040},
+		{1, 0, 0x0040},
+		{1, 1, 0x0040},
+		{1, 1, 0x0040},
+		{1, 2, 0x0040},
+		{1, 2, 0x0040},
+		{1, 3, 0x0040},
+		{0, 3, 0x0040},
+		{0, 4, 0x0040},
+		{0, 4, 0x0040},
+		{0, 5, 0x0040},
+		{0, 5, 0x0040},
+		{0, 6, 0x0040},
+		{0, 6, 0x0040},	}"
+
 	device domain 0 on
 		device ref host_bridge on  end	# Host bridge
 		device ref peg10 off end	# PCIe Bridge for discrete graphics
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index e7b936ae35d..d0decb4602e 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -1,44 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/hpet.h>
 #include <stdint.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#if CONFIG(USE_NATIVE_RAMINIT)
-#include <northbridge/intel/sandybridge/raminit_native.h>
-#else
 #include <northbridge/intel/sandybridge/raminit.h>
-#endif
 #include <southbridge/intel/bd82x6x/pch.h>
 
-#if !CONFIG(USE_NATIVE_RAMINIT)
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 0,
-		.gbe_enable = 1,
-		.max_ddr3_freq = 1333,
-		.usb_port_config = {
-#define USB_CONFIG(enabled, current, ocpin) { enabled, ocpin, 0x040 * current }
-#include "usb.h"
-		},
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xa0, 0x00, 0xa2, 0x00};
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
 }
-#endif
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index ea17cc8cce5..a7f5d3bd3ef 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -11,6 +11,23 @@ chip northbridge/intel/sandybridge
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
+	register "max_mem_clock_mhz" = "800"
+
+	register "usb_port_config" = "{
+		{ 1, 0, 0x0040 },
+		{ 1, 1, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 2, 0x0040 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 0, 4, 0x0000 },
+		{ 1, 6, 0x0040 },
+		{ 1, 5, 0x0040 }, }"
 
 	chip cpu/intel/model_206ax
 		device cpu_cluster 0 on end
diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c
index c697ef2bf36..853add4dd62 100644
--- a/src/mainboard/intel/emeraldlake2/early_init.c
+++ b/src/mainboard/intel/emeraldlake2/early_init.c
@@ -50,44 +50,9 @@ void bootblock_mainboard_early_init(void)
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 0,
-		.max_ddr3_freq = 1600,
-		.usb_port_config = {
-			{ 1, 0, 0x0040 }, /* P0: Front port  (OC0) */
-			{ 1, 1, 0x0040 }, /* P1: Back port   (OC1) */
-			{ 1, 0, 0x0040 }, /* P2: MINIPCIE1   (no OC) */
-			{ 1, 0, 0x0040 }, /* P3: MMC         (no OC) */
-			{ 1, 2, 0x0040 }, /* P4: Front port  (OC2) */
-			{ 0, 0, 0x0000 }, /* P5: Empty */
-			{ 0, 0, 0x0000 }, /* P6: Empty */
-			{ 0, 0, 0x0000 }, /* P7: Empty */
-			{ 1, 4, 0x0040 }, /* P8: Back port   (OC4) */
-			{ 1, 4, 0x0040 }, /* P9: MINIPCIE3   (no OC) */
-			{ 1, 4, 0x0040 }, /* P10: BLUETOOTH  (no OC) */
-			{ 0, 4, 0x0000 }, /* P11: Empty */
-			{ 1, 6, 0x0040 }, /* P12: Back port  (OC6) */
-			{ 1, 5, 0x0040 }, /* P13: Back port  (OC5) */
-		},
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = { 0xa0, 0x00, 0xa4, 0x00 };
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb
index e07cdf299e8..853a4102473 100644
--- a/src/mainboard/kontron/ktqm77/devicetree.cb
+++ b/src/mainboard/kontron/ktqm77/devicetree.cb
@@ -2,6 +2,29 @@ chip northbridge/intel/sandybridge
 	# IGD Displays
 	register "gfx" = "GMA_STATIC_DISPLAYS(0)"
 
+	register "max_mem_clock_mhz" = "800"
+	register "ec_present" = "1"
+
+	register "usb3.hs_port_switch_mask" = "0xf"
+	register "usb3.mode" = "3"
+	register "usb3.preboot_support" = "1"
+	register "usb3.xhci_streams" = "1"
+	register "usb_port_config" = "{
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 }, }"
+
 	chip cpu/intel/model_206ax
 		device cpu_cluster 0 on end
 
diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c
index 43cd7ac4754..e8fa6b1d69d 100644
--- a/src/mainboard/kontron/ktqm77/early_init.c
+++ b/src/mainboard/kontron/ktqm77/early_init.c
@@ -55,54 +55,9 @@ void bootblock_mainboard_early_init(void)
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, /* 0 Mobile, 1 Desktop/Server */
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 1,
-		.gbe_enable = 1,
-		.ddr3lv_support = 0,
-		.max_ddr3_freq = 1600,
-		.usb_port_config = {
-			 /* enabled   USB oc pin    length */
-			{ 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */
-			{ 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */
-			{ 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */
-			{ 1, 0, 0x0040 }, /* P3: upper right USB 3.0 (OC0) */
-			{ 1, 0, 0x0040 }, /* P4: lower USB 2.0 (OC0) */
-			{ 1, 0, 0x0040 }, /* P5: upper USB 2.0 (OC0) */
-			{ 1, 0, 0x0040 }, /* P6: front panel USB 2.0 (OC0) */
-			{ 1, 0, 0x0040 }, /* P7: front panel USB 2.0 (OC0) */
-			{ 1, 4, 0x0040 }, /* P8: internal USB 2.0 (OC4) */
-			{ 1, 4, 0x0040 }, /* P9: internal USB 2.0 (OC4) */
-			{ 1, 4, 0x0040 }, /* P10: internal USB 2.0 (OC4) */
-			{ 1, 4, 0x0040 }, /* P11: internal USB 2.0 (OC4) */
-			{ 1, 4, 0x0040 }, /* P12: internal USB 2.0 (OC4) */
-			{ 1, 4, 0x0040 }, /* P13: internal USB 2.0 (OC4) */
-		},
-		.usb3 = {
-			.mode =			3,	/* Smart Auto? */
-			.hs_port_switch_mask =	0xf,	/* All four ports. */
-			.preboot_support =	1,	/* preOS driver? */
-			.xhci_streams =		1,	/* Enable. */
-		},
-		.pcie_init = 1,
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00};
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 7a9959931e4..049eea6d84e 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -15,6 +15,25 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x1155"
 	register "gpu_pch_backlight" = "0x06100610"
 
+	register "ec_present" = "1"		# I have an embedded controller
+	register "max_mem_clock_mhz" = "666"	# So DDR3 freq = 1333
+
+	register "usb_port_config" = "{
+		{ 1, 0, 0x0040 },
+		{ 1, 1, 0x0080 },
+		{ 1, 3, 0x0080 },
+		{ 1, 3, 0x0080 },
+		{ 1, 0, 0x0080 },
+		{ 1, 0, 0x0080 },
+		{ 1, 2, 0x0040 },
+		{ 1, 2, 0x0040 },
+		{ 1, 6, 0x0080 },
+		{ 1, 5, 0x0080 },
+		{ 1, 6, 0x0080 },
+		{ 1, 6, 0x0080 },
+		{ 1, 7, 0x0080 },
+		{ 1, 6, 0x0080 },}"
+
 	device domain 0 on
 		subsystemid 0x17aa 0x21db inherit
 
diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c
index 78112eb9b0d..8edb0dd735d 100644
--- a/src/mainboard/lenovo/x220/early_init.c
+++ b/src/mainboard/lenovo/x220/early_init.c
@@ -9,45 +9,9 @@
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xa0, 0x00,0xa2,0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 1,
-		.gbe_enable = 1,
-		.max_ddr3_freq = 1333,
-		.usb_port_config = {
-			{ 1, 0, 0x0040 },
-			{ 1, 1, 0x0080 },
-			{ 1, 3, 0x0080 },
-			{ 1, 3, 0x0080 },
-			{ 1, 0, 0x0080 },
-			{ 1, 0, 0x0080 },
-			{ 1, 2, 0x0040 },
-			{ 1, 2, 0x0040 },
-			{ 1, 6, 0x0080 },
-			{ 1, 5, 0x0080 },
-			{ 1, 6, 0x0080 },
-			{ 1, 6, 0x0080 },
-			{ 1, 7, 0x0080 },
-			{ 1, 6, 0x0080 },
-		},
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xa0, 0x00, 0xa2, 0x00};
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
 }
 
 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
index 81037e85867..0e952b7a284 100644
--- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
+++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
@@ -17,6 +17,30 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x0000001a"
 	register "gpu_pch_backlight" = "0x002e0000"
 
+	register "usb3.mode" = "3"
+	register "usb3.hs_port_switch_mask" = "0xf"
+	register "usb3.preboot_support" = "1"
+	register "usb3.xhci_streams" = "1"
+
+	register "ec_present" = "1"
+	register "max_mem_clock_mhz" = "800"
+
+	register "usb_port_config" = "{
+		{ 1, 0, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 1, 1, 0x0080 },
+		{ 1, 2, 0x0080 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 3, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 5, 0x0040 }, }"
+
 	chip cpu/intel/model_206ax
 		device cpu_cluster 0 on end
 
diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c
index 9386620c537..328de9d0226 100644
--- a/src/mainboard/roda/rv11/variants/rv11/early_init.c
+++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c
@@ -9,54 +9,12 @@
 
 void mainboard_fill_pei_data(struct pei_data *const pei_data)
 {
-	const struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 1,
-		.gbe_enable = 1,
-		.ddr3lv_support = 0,
-		.max_ddr3_freq = 1600,
-		.usb_port_config = {
-			/* Enabled / OC PIN / Length */
-			{ 1, 0, 0x0040 }, /* P00: 1st            USB3 (OC #0) */
-			{ 1, 4, 0x0040 }, /* P01: 2nd            USB3 (OC #4) */
-			{ 1, 1, 0x0080 }, /* P02: 1st Multibay   USB3 (OC #1) */
-			{ 1, 2, 0x0080 }, /* P03: 2nd Multibay   USB3 (OC #2) */
-			{ 1, 8, 0x0040 }, /* P04: MiniPCIe 1     USB2 (no OC) */
-			{ 1, 8, 0x0040 }, /* P05: MiniPCIe 2     USB2 (no OC) */
-			{ 1, 8, 0x0040 }, /* P06: MiniPCIe 3     USB2 (no OC) */
-			{ 1, 8, 0x0040 }, /* P07: GPS            USB2 (no OC) */
-			{ 1, 8, 0x0040 }, /* P08: MiniPCIe 4     USB2 (no OC) */
-			{ 1, 3, 0x0040 }, /* P09: Express Card   USB2 (OC #3) */
-			{ 1, 8, 0x0040 }, /* P10: SD card reader USB2 (no OC) */
-			{ 1, 8, 0x0040 }, /* P11: Sensors Hub?   USB2 (no OC) */
-			{ 1, 8, 0x0040 }, /* P12: Touch Screen   USB2 (no OC) */
-			{ 1, 5, 0x0040 }, /* P13: reserved?      USB2 (OC #5) */
-		},
-		.usb3 = {
-			.mode =			3,	/* Smart Auto? */
-			.hs_port_switch_mask =	0xf,	/* All four ports. */
-			.preboot_support =	1,	/* preOS driver? */
-			.xhci_streams =		1,	/* Enable. */
-		},
-		.pcie_init = 1,
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xA0, 0x00, 0xA4, 0x00};
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+	/* TODO: Confirm if need to enable peg10 in devicetree */
+	pei_data->pcie_init = 1;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
index 79c182ee912..d2c38f3c106 100644
--- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
+++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
@@ -17,6 +17,29 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x00000ac8"
 	register "gpu_pch_backlight" = "0x13120000"
 
+	register "ec_present" = "1"
+	register "max_mem_clock_mhz" = "800"
+
+	register "usb3.mode" = "3"
+	register "usb3.hs_port_switch_mask" = "0xf"
+	register "usb3.preboot_support" = "1"
+	register "usb3.xhci_streams" = "1"
+	register "usb_port_config" = "{
+		{ 1, 0, 0x0080 },
+		{ 1, 0, 0x0080 },
+		{ 1, 1, 0x0080 },
+		{ 1, 1, 0x0080 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0080 },
+		{ 1, 4, 0x0080 },
+		{ 1, 5, 0x0040 },
+		{ 1, 8, 0x0040 },
+		{ 1, 8, 0x0080 },
+		{ 1, 6, 0x0080 }, }"
+
 	chip cpu/intel/model_206ax
 		device cpu_cluster 0 on end
 
diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c
index b3378ba4285..ffe095d23c7 100644
--- a/src/mainboard/roda/rv11/variants/rw11/early_init.c
+++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c
@@ -39,54 +39,12 @@ void bootblock_mainboard_early_init(void)
 
 void mainboard_fill_pei_data(struct pei_data *const pei_data)
 {
-	const struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 1,
-		.gbe_enable = 1,
-		.ddr3lv_support = 0,
-		.max_ddr3_freq = 1600,
-		.usb_port_config = {
-			/* Enabled / OC PIN / Length */
-			{ 1, 0, 0x0080 }, /* P00: 1st (left)     USB3 (OC #0) */
-			{ 1, 0, 0x0080 }, /* P01: 2nd (left)     USB3 (OC #0) */
-			{ 1, 1, 0x0080 }, /* P02: 1st Multibay   USB3 (OC #1) */
-			{ 1, 1, 0x0080 }, /* P03: 2nd Multibay   USB3 (OC #1) */
-			{ 1, 8, 0x0040 }, /* P04: MiniPCIe 1     USB2 (no OC) */
-			{ 1, 8, 0x0040 }, /* P05: MiniPCIe 2     USB2 (no OC) */
-			{ 1, 8, 0x0040 }, /* P06: USB Hub x4     USB2 (no OC) */
-			{ 1, 8, 0x0040 }, /* P07: MiniPCIe 4     USB2 (no OC) */
-			{ 1, 8, 0x0080 }, /* P08: SD card reader USB2 (no OC) */
-			{ 1, 4, 0x0080 }, /* P09: 3rd (right)    USB2 (OC #4) */
-			{ 1, 5, 0x0040 }, /* P10: 4th (right)    USB2 (OC #5) */
-			{ 1, 8, 0x0040 }, /* P11: 3rd Multibay   USB2 (no OC) */
-			{ 1, 8, 0x0080 }, /* P12: misc internal  USB2 (no OC) */
-			{ 1, 6, 0x0080 }, /* P13: misc internal  USB2 (OC #6) */
-		},
-		.usb3 = {
-			.mode =			3,	/* Smart Auto? */
-			.hs_port_switch_mask =	0xf,	/* All four ports. */
-			.preboot_support =	1,	/* preOS driver? */
-			.xhci_streams =		1,	/* Enable. */
-		},
-		.pcie_init = 1,
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xA0, 0xA2, 0xA4, 0xA6};
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+	/* TODO: Confirm if need to enable peg10 in devicetree */
+	pei_data->pcie_init = 1;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index febaade15fc..a8efd67da44 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -17,8 +17,25 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x000001e8"
 	register "gpu_pch_backlight" = "0x03d00000"
 
+	register "ec_present" = "1"
 	register "max_mem_clock_mhz" = "666"
 
+	register "usb_port_config" = "{
+		{ 1, 0, 0x0080 },
+		{ 1, 1, 0x0080 },
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 1, 4, 0x0040 },
+		{ 0, 4, 0x0000 },
+		{ 0, 4, 0x0000 },
+		{ 1, 4, 0x0040 },
+		{ 0, 4, 0x0000 },
+		{ 0, 4, 0x0000 },}"
+
 	device domain 0 on
 		subsystemid 0x1ae0 0xc000 inherit
 		device ref host_bridge on end # host bridge
diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c
index 3f515ec3745..495d04eae88 100644
--- a/src/mainboard/samsung/lumpy/early_init.c
+++ b/src/mainboard/samsung/lumpy/early_init.c
@@ -115,44 +115,13 @@ static const uint8_t *locate_spd(void)
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xa0, 0x00,0x00,0x00 },
-		.ts_addresses = { 0x30, 0x00, 0x00, 0x00 },
-		.ec_present = 1,
-		.max_ddr3_freq = 1333,
-		.usb_port_config = {
-			{ 1, 0, 0x0080 }, /* P0: Port 0      (OC0) */
-			{ 1, 1, 0x0080 }, /* P1: Port 1      (OC1) */
-			{ 1, 0, 0x0040 }, /* P2: MINIPCIE1   (no OC) */
-			{ 1, 0, 0x0040 }, /* P3: MMC         (no OC) */
-			{ 0, 0, 0x0000 }, /* P4: Empty */
-			{ 0, 0, 0x0000 }, /* P5: Empty */
-			{ 0, 0, 0x0000 }, /* P6: Empty */
-			{ 0, 0, 0x0000 }, /* P7: Empty */
-			{ 1, 4, 0x0040 }, /* P8: MINIPCIE2   (no OC) */
-			{ 0, 4, 0x0000 }, /* P9: Empty */
-			{ 0, 4, 0x0000 }, /* P10: Empty */
-			{ 1, 4, 0x0040 }, /* P11: Camera     (no OC) */
-			{ 0, 4, 0x0000 }, /* P12: Empty */
-			{ 0, 4, 0x0000 }, /* P13: Empty */
-		},
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xa0, 0x00, 0x00, 0x00};
+	const uint8_t tsaddr[] = {0x30, 0x00, 0x00, 0x00};
+
+	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+	/* Only this board uses .ts_addresses. Fill here to allow removal from devicetree. */
+	memcpy(pei_data->ts_addresses, &tsaddr, sizeof(pei_data->ts_addresses));
 	memcpy(pei_data->spd_data[2], locate_spd(), 256);
 }
 
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index 4147b160d46..6847726308e 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -11,6 +11,22 @@ chip northbridge/intel/sandybridge
 
 	register "max_mem_clock_mhz" = "666"
 
+	register "usb_port_config" = "{
+		{ 1, 0, 0x0080 },
+		{ 1, 1, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 0, 0x0040 },
+		{ 1, 2, 0x0080 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 0, 0, 0x0000 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 1, 4, 0x0040 },
+		{ 0, 4, 0x0000 },
+		{ 1, 6, 0x0040 },
+		{ 1, 5, 0x0040 }, }"
+
 	chip cpu/intel/model_206ax
 		device cpu_cluster 0 on end
 
diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c
index 14fc2528d92..d4c1cc51664 100644
--- a/src/mainboard/samsung/stumpy/early_init.c
+++ b/src/mainboard/samsung/stumpy/early_init.c
@@ -91,44 +91,11 @@ static void setup_sio_gpios(void)
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xa0, 0x00,0xa4,0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 0,
-		.max_ddr3_freq = 1333,
-		.usb_port_config = {
-			{ 1, 0, 0x0080 }, /* P0: Front port  (OC0) */
-			{ 1, 1, 0x0040 }, /* P1: Back port   (OC1) */
-			{ 1, 0, 0x0040 }, /* P2: MINIPCIE1   (no OC) */
-			{ 1, 0, 0x0040 }, /* P3: MMC         (no OC) */
-			{ 1, 2, 0x0080 }, /* P4: Front port  (OC2) */
-			{ 0, 0, 0x0000 }, /* P5: Empty */
-			{ 0, 0, 0x0000 }, /* P6: Empty */
-			{ 0, 0, 0x0000 }, /* P7: Empty */
-			{ 1, 4, 0x0040 }, /* P8: Back port   (OC4) */
-			{ 1, 4, 0x0040 }, /* P9: MINIPCIE3   (no OC) */
-			{ 1, 4, 0x0040 }, /* P10: BLUETOOTH  (no OC) */
-			{ 0, 4, 0x0000 }, /* P11: Empty */
-			{ 1, 6, 0x0040 }, /* P12: Back port  (OC6) */
-			{ 1, 5, 0x0040 }, /* P13: Back port  (OC5) */
-		},
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xa0, 0x00, 0xa4, 0x00};
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
 }
 
 void mainboard_get_spd(spd_raw_data *spd, bool id_only)