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route all pins for R2

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1 parent 87c9d27 commit 851f8d22ac5ae3c08aabc0ad491aafd38cd3fc61 @corecode committed Feb 19, 2012
Showing with 12,283 additions and 9,929 deletions.
  1. +1 −1 hardware/STM32L15x_QFN48.dcm
  2. +9 −9 hardware/STM32L15x_QFN48.lib
  3. +55 −0 hardware/SparkFun-SJ_2.mod
  4. +9,437 −9,299 hardware/mchck.brd
  5. +28 −14 hardware/mchck.cmp
  6. +1,790 −0 hardware/mchck.mod
  7. +297 −266 hardware/mchck.net
  8. +34 −32 hardware/mchck.pro
  9. +608 −286 hardware/mchck.sch
  10. +24 −22 hardware/power.sch
@@ -1,3 +1,3 @@
-EESchema-DOCLIB Version 2.0 Date: Sun 05 Feb 2012 09:51:25 PM CET
+EESchema-DOCLIB Version 2.0 Date: Sun 05 Feb 2012 11:29:05 PM CET
#
#End Doc Library
@@ -1,4 +1,4 @@
-EESchema-LIBRARY Version 2.3 Date: Sun 05 Feb 2012 09:51:25 PM CET
+EESchema-LIBRARY Version 2.3 Date: Sun 05 Feb 2012 11:29:05 PM CET
#encoding utf-8
#
# STM32L15x_QFN48
@@ -7,15 +7,15 @@ DEF STM32L15x_QFN48 U 0 40 Y Y 1 F N
F0 "U" 0 -100 50 H V C CNN
F1 "STM32L15x_QFN48" 0 100 50 H V C CNN
DRAW
-T 0 -300 750 60 0 0 0 I2C Normal 0 C C
-T 0 0 750 60 0 0 0 I2C Normal 0 C C
-T 0 300 -700 60 0 0 0 I2C Normal 0 C C
-T 0 -300 -800 60 0 0 0 SPI Normal 0 C C
-T 0 300 450 60 0 0 0 SPI Normal 0 C C
-T 900 750 -400 60 0 0 0 SPI Normal 0 C C
+T 0 -300 750 60 0 0 0 I2C1 Normal 0 C C
+T 0 0 750 60 0 0 0 I2C1 Normal 0 C C
+T 0 300 -700 60 0 0 0 I2C2 Normal 0 C C
+T 0 -300 -800 60 0 0 0 SPI1 Normal 0 C C
+T 0 300 450 60 0 0 0 SPI1 Normal 0 C C
+T 900 750 -400 60 0 0 0 SPI2 Normal 0 C C
T 900 650 550 60 0 0 0 SWD Normal 0 C C
-T 0 -800 -700 60 0 0 0 USART Italic 0 C C
-T 0 650 0 60 0 0 0 USART Normal 0 C C
+T 0 650 0 60 0 0 0 USART1 Normal 0 C C
+T 0 -800 -700 60 0 0 0 USART2 Normal 0 C C
T 900 450 200 60 0 0 0 USB Normal 0 C C
S -1050 -1050 1050 1050 0 0 0 N
S -200 1050 -400 700 0 0 0 f
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