counter is a 4-bit register that holds the state of the ring counter.
The always block is sensitive to the rising edge of the clock ( posedge clk ) and the rising edge of the reset signal ( posedge rst ).
When the reset signal (rst) is asserted, the counter is initialized to 4'b0001.
When not in reset, the counter is shifted one position to the left ( counter << 1 ), and the MSB (Most Significant Bit) is connected to the LSB (Least Significant Bit) to create the ring effect.
The assign statement assigns the current state of the counter register to the output out.
You can modify the number of bits by changing the bit width of the counter and out signals.
We instantiate the Ring_Counter_tb.v module and connect its ports to signals within the testbench.
We generate a clock signal ( clk ) with a 50% duty cycle. The clock signal alternates between 0 and 1 with a delay of 5 time units between transitions.
We initialize the rst signal to 1 for 10 time units to reset the counter and then set it to 0 to start counting.
The $display and $monitor statements are used to display the time and the state of the ring counter at each time step.
The simulation runs for 20 clock cycles ( #100 time units) and then finishes.