This is a port of WTFpga to chisel3.
To get the timing report just run:
make
To run the Chisel3/Scala unit tests, use:
make test
To get timing results (i.e. maximum frequency), run:
make timing
To flash the device, run:
make flash
- Get VSCode
- Install the following extensions:
Task | Mill | SBT |
---|---|---|
make test (no change) |
7s | 16s |
- https://github.com/edwardcwang/chisel-multiclock-demo/
- https://github.com/freechipsproject/chisel-template/
- https://github.com/olafurpg/setup-scala
- https://github.com/open-tool-forge/fpga-toolchain
- https://stackoverflow.com/questions/40470153/is-there-a-simple-example-of-how-to-generate-verilog-from-chisel3-module
- https://stackoverflow.com/questions/41427717/how-to-delete-clock-signal-on-chisel3-top-module
- https://stackoverflow.com/questions/55209951/chisel3-how-to-create-a-register-without-reset-signal-in-rawmodule
- https://stackoverflow.com/questions/59407466/how-to-override-extend-chisel-signal-naming/59411596#59411596
- ucb-bar/chiseltest#61
- https://github.com/antonblanchard/chiselwatt/blob/e2c513555d025684a15c584ef96bed02cc30ca40/build.sc