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Moved backends from procs folder to backends folder
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acw1251 committed Apr 26, 2017
1 parent f7b91ef commit 0e0f007
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Showing 36 changed files with 27 additions and 23 deletions.
8 changes: 6 additions & 2 deletions .gitignore
@@ -1,12 +1,16 @@
# compiled toolchains
/tools/RV*

# generated directories and executables
# generated directories and files
verilator
!/procs/verilator
!/backends/verilator
accelerator
!/accelerator
build
out
/tools/elf2hex/elf2hex
*.exe
generatedDesignInterfaceFile.json

# hex files
*.hex
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24 changes: 12 additions & 12 deletions procs/connectal/Makefile → backends/connectal/Makefile
Expand Up @@ -48,25 +48,25 @@ endif
BSVPATH += \
$(RISCY_HOME)/procs/riscy-lib \
$(RISCY_HOME)/procs/$(PROC) \
$(RISCY_HOME)/procs/connectal/bsv \
$(RISCY_HOME)/backends/connectal/bsv \
$(RISCY_HOME)/recycle-bsv-lib/src/bsv \

BSVFILES += \
$(RISCY_HOME)/procs/connectal/bsv/ProcConnectal.bsv \
$(RISCY_HOME)/procs/riscy-lib/ProcPins.bsv \
$(RISCY_HOME)/procs/riscy-lib/VerificationPacket.bsv \
$(RISCY_HOME)/backends/connectal/bsv/ProcConnectal.bsv \
$(RISCY_HOME)/recycle-bsv-lib/src/bsv/PerfMonitorConnectal.bsv \

CPPFILES += \
$(RISCY_HOME)/procs/connectal/cpp/testproc.cpp \
$(RISCY_HOME)/procs/connectal/cpp/Platform.cpp \
$(RISCY_HOME)/procs/connectal/cpp/ProcControl.cpp \
$(RISCY_HOME)/procs/connectal/cpp/Verification.cpp \
$(RISCY_HOME)/procs/connectal/cpp/ExternalMMIO.cpp \
$(RISCY_HOME)/procs/connectal/cpp/SpikeTandemVerifier.cpp \
$(RISCY_HOME)/procs/connectal/cpp/PrintTrace.cpp \
$(RISCY_HOME)/procs/connectal/cpp/ElfLoader.cpp \
$(RISCY_HOME)/procs/connectal/cpp/UartBridge.cpp \
$(RISCY_HOME)/backends/connectal/cpp/testproc.cpp \
$(RISCY_HOME)/backends/connectal/cpp/Platform.cpp \
$(RISCY_HOME)/backends/connectal/cpp/ProcControl.cpp \
$(RISCY_HOME)/backends/connectal/cpp/Verification.cpp \
$(RISCY_HOME)/backends/connectal/cpp/ExternalMMIO.cpp \
$(RISCY_HOME)/backends/connectal/cpp/SpikeTandemVerifier.cpp \
$(RISCY_HOME)/backends/connectal/cpp/PrintTrace.cpp \
$(RISCY_HOME)/backends/connectal/cpp/ElfLoader.cpp \
$(RISCY_HOME)/backends/connectal/cpp/UartBridge.cpp \
$(RISCY_HOME)/recycle-bsv-lib/src/cpp/PerfMonitor.cpp \
$(CONNECTALDIR)/cpp/DmaBuffer.cpp \

Expand All @@ -93,7 +93,7 @@ MEM_WRITE_INTERFACES = \

NUMBER_OF_MASTERS = 1

PINOUT_FILE += $(RISCY_HOME)/procs/connectal/pin_translation.json
PINOUT_FILE += $(RISCY_HOME)/backends/connectal/pin_translation.json
PIN_TYPE = ProcPins
PIN_TYPE_INCLUDE = ProcPins
AUTOTOP = --interface pins:ProcConnectal.pins
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6 changes: 3 additions & 3 deletions procs/verilator/Makefile → backends/verilator/Makefile
Expand Up @@ -33,7 +33,7 @@ endif
VERILATOR_EXE=$(PROC).exe

TOP_MODULE=mkProcVerilator
TOP_BSV_FILE=$(RISCY_HOME)/procs/verilator/bsv/ProcVerilator.bsv
TOP_BSV_FILE=$(RISCY_HOME)/backends/verilator/bsv/ProcVerilator.bsv

# Build Directories
BUILD_DIR=build
Expand All @@ -43,14 +43,14 @@ VERILATOR_DIR=$(BUILD_DIR)/verilator



BSV_PATH = $(RISCY_HOME)/procs/riscy-lib:$(RISCY_HOME)/procs/$(PROC):$(RISCY_HOME)/procs/verilator/bsv:$(RISCY_HOME)/recycle-bsv-lib/src/bsv:+
BSV_PATH = $(RISCY_HOME)/procs/riscy-lib:$(RISCY_HOME)/procs/$(PROC):$(RISCY_HOME)/backends/verilator/bsv:$(RISCY_HOME)/recycle-bsv-lib/src/bsv:+
BSC_DEFINES += -D CONFIG_IDMEM_INIT_HEX_FILE=\"idmem.hex\"
BSC_DEFINES += -D CONFIG_RAM_INIT_HEX_FILE=\"ram.hex\"
BSC_FLAGS = -aggressive-conditions -keep-fires $(BSC_DEFINES) -p $(BSV_PATH) -bdir $(BSC_DIR) -fdir $(BSC_DIR) -info-dir $(BSC_DIR) -simdir $(BSC_DIR) -vdir $(VERILOG_DIR)

VERILOG_PATH = -y $(BLUESPECDIR)/Verilog -y $(VERILOG_DIR)
VERILATOR_FLAGS = -Mdir $(VERILATOR_DIR) -CFLAGS -O2 $(VERILOG_PATH) -Wno-fatal --trace
VERILATOR_CPP = $(RISCY_HOME)/procs/verilator/cpp/verilator_top.cpp
VERILATOR_CPP = $(RISCY_HOME)/backends/verilator/cpp/verilator_top.cpp

.PHONY: verilator verilog clean

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6 changes: 3 additions & 3 deletions procs/RV32IM_3stage/Makefile
Expand Up @@ -52,12 +52,12 @@ CONNECTALFLAGS += -D CONFIG_SPI

ifdef RISCY_HOME
ifeq ($(MAKECMDGOALS),verilator)
include $(RISCY_HOME)/procs/verilator/Makefile
include $(RISCY_HOME)/backends/verilator/Makefile
else ifeq ($(MAKECMDGOALS),verilog)
include $(RISCY_HOME)/procs/verilator/Makefile
include $(RISCY_HOME)/backends/verilator/Makefile
else
# connectal backend
include $(RISCY_HOME)/procs/connectal/Makefile
include $(RISCY_HOME)/backends/connectal/Makefile
endif
else
$(error RISCY_HOME is undefined)
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6 changes: 3 additions & 3 deletions procs/RV64G_multicycle/Makefile
Expand Up @@ -42,12 +42,12 @@ CONNECTALFLAGS += -D CONFIG_D

ifdef RISCY_HOME
ifeq ($(MAKECMDGOALS),verilator)
include $(RISCY_HOME)/procs/verilator/Makefile
include $(RISCY_HOME)/backends/verilator/Makefile
else ifeq ($(MAKECMDGOALS),verilog)
include $(RISCY_HOME)/procs/verilator/Makefile
include $(RISCY_HOME)/backends/verilator/Makefile
else
# connectal backend
include $(RISCY_HOME)/procs/connectal/Makefile
include $(RISCY_HOME)/backends/connectal/Makefile
endif
else
$(error RISCY_HOME is undefined)
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