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prabhakarladgeertu
prabhakarlad
authored and
geertu
committed
pinctrl: renesas: rzg2l: Rename PIN_CFG_* macros to match HW manual
Rename the below macros to match the HW manual (Rev.1.00): PIN_CFG_IOLH_SD0 -> PIN_CFG_IO_VMC_SD0 PIN_CFG_IOLH_SD1 -> PIN_CFG_IO_VMC_SD1 PIN_CFG_IOLH_QSPI -> PIN_CFG_IO_VMC_QSPI PIN_CFG_IOLH_ETH0 -> PIN_CFG_IO_VMC_ETH0 PIN_CFG_IOLH_ETH1 -> PIN_CFG_IO_VMC_ETH1 Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211110224622.16022-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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‎drivers/pinctrl/renesas/pinctrl-rzg2l.c‎

Lines changed: 61 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -39,11 +39,11 @@
3939
#define PIN_CFG_SR BIT(1)
4040
#define PIN_CFG_IEN BIT(2)
4141
#define PIN_CFG_PUPD BIT(3)
42-
#define PIN_CFG_IOLH_SD0 BIT(4)
43-
#define PIN_CFG_IOLH_SD1 BIT(5)
44-
#define PIN_CFG_IOLH_QSPI BIT(6)
45-
#define PIN_CFG_IOLH_ETH0 BIT(7)
46-
#define PIN_CFG_IOLH_ETH1 BIT(8)
42+
#define PIN_CFG_IO_VMC_SD0 BIT(4)
43+
#define PIN_CFG_IO_VMC_SD1 BIT(5)
44+
#define PIN_CFG_IO_VMC_QSPI BIT(6)
45+
#define PIN_CFG_IO_VMC_ETH0 BIT(7)
46+
#define PIN_CFG_IO_VMC_ETH1 BIT(8)
4747
#define PIN_CFG_FILONOFF BIT(9)
4848
#define PIN_CFG_FILNUM BIT(10)
4949
#define PIN_CFG_FILCLKSEL BIT(11)
@@ -516,11 +516,11 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
516516
case PIN_CONFIG_POWER_SOURCE: {
517517
u32 pwr_reg = 0x0;
518518

519-
if (cfg & PIN_CFG_IOLH_SD0)
519+
if (cfg & PIN_CFG_IO_VMC_SD0)
520520
pwr_reg = SD_CH(0);
521-
else if (cfg & PIN_CFG_IOLH_SD1)
521+
else if (cfg & PIN_CFG_IO_VMC_SD1)
522522
pwr_reg = SD_CH(1);
523-
else if (cfg & PIN_CFG_IOLH_QSPI)
523+
else if (cfg & PIN_CFG_IO_VMC_QSPI)
524524
pwr_reg = QSPI;
525525
else
526526
return -EINVAL;
@@ -594,11 +594,11 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
594594
if (mV != 1800 && mV != 3300)
595595
return -EINVAL;
596596

597-
if (cfg & PIN_CFG_IOLH_SD0)
597+
if (cfg & PIN_CFG_IO_VMC_SD0)
598598
pwr_reg = SD_CH(0);
599-
else if (cfg & PIN_CFG_IOLH_SD1)
599+
else if (cfg & PIN_CFG_IO_VMC_SD1)
600600
pwr_reg = SD_CH(1);
601-
else if (cfg & PIN_CFG_IOLH_QSPI)
601+
else if (cfg & PIN_CFG_IO_VMC_QSPI)
602602
pwr_reg = QSPI;
603603
else
604604
return -EINVAL;
@@ -900,24 +900,24 @@ static const u32 rzg2l_gpio_configs[] = {
900900
RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
901901
RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
902902
RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
903-
RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
904-
RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
905-
RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
906-
RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
907-
RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
908-
RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
909-
RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
910-
RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
911-
RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)),
912-
RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
913-
RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
914-
RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
915-
RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
916-
RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
917-
RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
918-
RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
919-
RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
920-
RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH1)),
903+
RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
904+
RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
905+
RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
906+
RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
907+
RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
908+
RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
909+
RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
910+
RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
911+
RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
912+
RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
913+
RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
914+
RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
915+
RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
916+
RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
917+
RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
918+
RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
919+
RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
920+
RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
921921
RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
922922
RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
923923
RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
@@ -941,68 +941,68 @@ static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
941941
{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
942942
{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
943943
{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
944-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) },
944+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
945945
{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
946-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
946+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
947947
{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
948-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD0)) },
948+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
949949
{ "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
950-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
950+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
951951
{ "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
952-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
952+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
953953
{ "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
954-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
954+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
955955
{ "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
956-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
956+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
957957
{ "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
958-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
958+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
959959
{ "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
960-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
960+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
961961
{ "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
962-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
962+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
963963
{ "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
964-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD0)) },
964+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
965965
{ "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
966-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_SD1))},
966+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1))},
967967
{ "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
968-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
968+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
969969
{ "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
970-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
970+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
971971
{ "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
972-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
972+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
973973
{ "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
974-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
974+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
975975
{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
976-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IOLH_SD1)) },
976+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
977977
{ "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
978-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
978+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
979979
{ "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
980-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
980+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
981981
{ "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
982-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
982+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
983983
{ "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
984-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
984+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
985985
{ "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
986-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
986+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
987987
{ "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
988-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
988+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
989989
{ "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
990-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
990+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
991991
{ "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
992-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
992+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
993993
{ "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
994-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
994+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
995995
{ "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
996-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
996+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
997997
{ "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
998-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
998+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
999999
{ "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
1000-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
1000+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
10011001
{ "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
1002-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
1002+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
10031003
{ "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
1004-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
1005-
{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IOLH_QSPI)) },
1004+
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1005+
{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
10061006
{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH | PIN_CFG_SR)) },
10071007
{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
10081008
{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },

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