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x86/mce: Break up __mcheck_cpu_apply_quirks()
Split each vendor specific part into its own helper function. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Sohil Mehta <sohil.mehta@intel.com> Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com> Tested-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://lore.kernel.org/r/20241212140103.66964-5-qiuxu.zhuo@intel.com
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‎arch/x86/kernel/cpu/mce/core.c‎

Lines changed: 92 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -1910,101 +1910,117 @@ static void __mcheck_cpu_check_banks(void)
19101910
}
19111911
}
19121912

1913-
/* Add per CPU specific workarounds here */
1914-
static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1913+
static void apply_quirks_amd(struct cpuinfo_x86 *c)
19151914
{
19161915
struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1917-
struct mca_config *cfg = &mca_cfg;
1918-
1919-
if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1920-
pr_info("unknown CPU type - not enabling MCE support\n");
1921-
return false;
1922-
}
19231916

19241917
/* This should be disabled by the BIOS, but isn't always */
1925-
if (c->x86_vendor == X86_VENDOR_AMD) {
1926-
if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
1927-
/*
1928-
* disable GART TBL walk error reporting, which
1929-
* trips off incorrectly with the IOMMU & 3ware
1930-
* & Cerberus:
1931-
*/
1932-
clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1933-
}
1934-
if (c->x86 < 0x11 && cfg->bootlog < 0) {
1935-
/*
1936-
* Lots of broken BIOS around that don't clear them
1937-
* by default and leave crap in there. Don't log:
1938-
*/
1939-
cfg->bootlog = 0;
1940-
}
1918+
if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
19411919
/*
1942-
* Various K7s with broken bank 0 around. Always disable
1943-
* by default.
1920+
* disable GART TBL walk error reporting, which
1921+
* trips off incorrectly with the IOMMU & 3ware
1922+
* & Cerberus:
19441923
*/
1945-
if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
1946-
mce_banks[0].ctl = 0;
1924+
clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1925+
}
19471926

1927+
if (c->x86 < 0x11 && mca_cfg.bootlog < 0) {
19481928
/*
1949-
* overflow_recov is supported for F15h Models 00h-0fh
1950-
* even though we don't have a CPUID bit for it.
1929+
* Lots of broken BIOS around that don't clear them
1930+
* by default and leave crap in there. Don't log:
19511931
*/
1952-
if (c->x86 == 0x15 && c->x86_model <= 0xf)
1953-
mce_flags.overflow_recov = 1;
1932+
mca_cfg.bootlog = 0;
1933+
}
19541934

1955-
if (c->x86 >= 0x17 && c->x86 <= 0x1A)
1956-
mce_flags.zen_ifu_quirk = 1;
1935+
/*
1936+
* Various K7s with broken bank 0 around. Always disable
1937+
* by default.
1938+
*/
1939+
if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
1940+
mce_banks[0].ctl = 0;
19571941

1958-
}
1942+
/*
1943+
* overflow_recov is supported for F15h Models 00h-0fh
1944+
* even though we don't have a CPUID bit for it.
1945+
*/
1946+
if (c->x86 == 0x15 && c->x86_model <= 0xf)
1947+
mce_flags.overflow_recov = 1;
19591948

1960-
if (c->x86_vendor == X86_VENDOR_INTEL) {
1961-
/*
1962-
* SDM documents that on family 6 bank 0 should not be written
1963-
* because it aliases to another special BIOS controlled
1964-
* register.
1965-
* But it's not aliased anymore on model 0x1a+
1966-
* Don't ignore bank 0 completely because there could be a
1967-
* valid event later, merely don't write CTL0.
1968-
*/
1949+
if (c->x86 >= 0x17 && c->x86 <= 0x1A)
1950+
mce_flags.zen_ifu_quirk = 1;
1951+
}
19691952

1970-
if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
1971-
mce_banks[0].init = false;
1953+
static void apply_quirks_intel(struct cpuinfo_x86 *c)
1954+
{
1955+
struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
19721956

1973-
/*
1974-
* All newer Intel systems support MCE broadcasting. Enable
1975-
* synchronization with a one second timeout.
1976-
*/
1977-
if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1978-
cfg->monarch_timeout < 0)
1979-
cfg->monarch_timeout = USEC_PER_SEC;
1957+
/*
1958+
* SDM documents that on family 6 bank 0 should not be written
1959+
* because it aliases to another special BIOS controlled
1960+
* register.
1961+
* But it's not aliased anymore on model 0x1a+
1962+
* Don't ignore bank 0 completely because there could be a
1963+
* valid event later, merely don't write CTL0.
1964+
*/
1965+
if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
1966+
mce_banks[0].init = false;
19801967

1981-
/*
1982-
* There are also broken BIOSes on some Pentium M and
1983-
* earlier systems:
1984-
*/
1985-
if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1986-
cfg->bootlog = 0;
1968+
/*
1969+
* All newer Intel systems support MCE broadcasting. Enable
1970+
* synchronization with a one second timeout.
1971+
*/
1972+
if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1973+
mca_cfg.monarch_timeout < 0)
1974+
mca_cfg.monarch_timeout = USEC_PER_SEC;
1975+
1976+
/*
1977+
* There are also broken BIOSes on some Pentium M and
1978+
* earlier systems:
1979+
*/
1980+
if (c->x86 == 6 && c->x86_model <= 13 && mca_cfg.bootlog < 0)
1981+
mca_cfg.bootlog = 0;
19871982

1988-
if (c->x86_vfm == INTEL_SANDYBRIDGE_X)
1989-
mce_flags.snb_ifu_quirk = 1;
1983+
if (c->x86_vfm == INTEL_SANDYBRIDGE_X)
1984+
mce_flags.snb_ifu_quirk = 1;
19901985

1991-
/*
1992-
* Skylake, Cascacde Lake and Cooper Lake require a quirk on
1993-
* rep movs.
1994-
*/
1995-
if (c->x86_vfm == INTEL_SKYLAKE_X)
1996-
mce_flags.skx_repmov_quirk = 1;
1986+
/*
1987+
* Skylake, Cascacde Lake and Cooper Lake require a quirk on
1988+
* rep movs.
1989+
*/
1990+
if (c->x86_vfm == INTEL_SKYLAKE_X)
1991+
mce_flags.skx_repmov_quirk = 1;
1992+
}
1993+
1994+
static void apply_quirks_zhaoxin(struct cpuinfo_x86 *c)
1995+
{
1996+
/*
1997+
* All newer Zhaoxin CPUs support MCE broadcasting. Enable
1998+
* synchronization with a one second timeout.
1999+
*/
2000+
if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
2001+
if (mca_cfg.monarch_timeout < 0)
2002+
mca_cfg.monarch_timeout = USEC_PER_SEC;
19972003
}
2004+
}
19982005

1999-
if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
2000-
/*
2001-
* All newer Zhaoxin CPUs support MCE broadcasting. Enable
2002-
* synchronization with a one second timeout.
2003-
*/
2004-
if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
2005-
if (cfg->monarch_timeout < 0)
2006-
cfg->monarch_timeout = USEC_PER_SEC;
2007-
}
2006+
/* Add per CPU specific workarounds here */
2007+
static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
2008+
{
2009+
struct mca_config *cfg = &mca_cfg;
2010+
2011+
switch (c->x86_vendor) {
2012+
case X86_VENDOR_UNKNOWN:
2013+
pr_info("unknown CPU type - not enabling MCE support\n");
2014+
return false;
2015+
case X86_VENDOR_AMD:
2016+
apply_quirks_amd(c);
2017+
break;
2018+
case X86_VENDOR_INTEL:
2019+
apply_quirks_intel(c);
2020+
break;
2021+
case X86_VENDOR_ZHAOXIN:
2022+
apply_quirks_zhaoxin(c);
2023+
break;
20082024
}
20092025

20102026
if (cfg->monarch_timeout < 0)

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