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Kan LiangPeter Zijlstra
Kan Liang
authored and
Peter Zijlstra
committed
perf/x86/intel/uncore: Add Alder Lake support
The uncore subsystem for Alder Lake is similar to the previous Tiger Lake. The difference includes: - New MSR addresses for global control, fixed counters, CBOX and ARB. Add a new adl_uncore_msr_ops for uncore operations. - Add a new threshold field for CBOX. - New PCIIDs for IMC devices. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lkml.kernel.org/r/1618237865-33448-23-git-send-email-kan.liang@linux.intel.com
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‎arch/x86/events/intel/uncore.c‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1752,6 +1752,11 @@ static const struct intel_uncore_init_fun rkl_uncore_init __initconst = {
17521752
.pci_init = skl_uncore_pci_init,
17531753
};
17541754

1755+
static const struct intel_uncore_init_fun adl_uncore_init __initconst = {
1756+
.cpu_init = adl_uncore_cpu_init,
1757+
.mmio_init = tgl_uncore_mmio_init,
1758+
};
1759+
17551760
static const struct intel_uncore_init_fun icx_uncore_init __initconst = {
17561761
.cpu_init = icx_uncore_cpu_init,
17571762
.pci_init = icx_uncore_pci_init,
@@ -1806,6 +1811,8 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
18061811
X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &tgl_l_uncore_init),
18071812
X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &tgl_uncore_init),
18081813
X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &rkl_uncore_init),
1814+
X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &adl_uncore_init),
1815+
X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &adl_uncore_init),
18091816
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &snr_uncore_init),
18101817
{},
18111818
};

‎arch/x86/events/intel/uncore.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -582,6 +582,7 @@ void snb_uncore_cpu_init(void);
582582
void nhm_uncore_cpu_init(void);
583583
void skl_uncore_cpu_init(void);
584584
void icl_uncore_cpu_init(void);
585+
void adl_uncore_cpu_init(void);
585586
void tgl_uncore_cpu_init(void);
586587
void tgl_uncore_mmio_init(void);
587588
void tgl_l_uncore_mmio_init(void);

‎arch/x86/events/intel/uncore_snb.c‎

Lines changed: 131 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,8 @@
6262
#define PCI_DEVICE_ID_INTEL_TGL_H_IMC 0x9a36
6363
#define PCI_DEVICE_ID_INTEL_RKL_1_IMC 0x4c43
6464
#define PCI_DEVICE_ID_INTEL_RKL_2_IMC 0x4c53
65+
#define PCI_DEVICE_ID_INTEL_ADL_1_IMC 0x4660
66+
#define PCI_DEVICE_ID_INTEL_ADL_2_IMC 0x4641
6567

6668
/* SNB event control */
6769
#define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff
@@ -131,12 +133,33 @@
131133
#define ICL_UNC_ARB_PER_CTR 0x3b1
132134
#define ICL_UNC_ARB_PERFEVTSEL 0x3b3
133135

136+
/* ADL uncore global control */
137+
#define ADL_UNC_PERF_GLOBAL_CTL 0x2ff0
138+
#define ADL_UNC_FIXED_CTR_CTRL 0x2fde
139+
#define ADL_UNC_FIXED_CTR 0x2fdf
140+
141+
/* ADL Cbo register */
142+
#define ADL_UNC_CBO_0_PER_CTR0 0x2002
143+
#define ADL_UNC_CBO_0_PERFEVTSEL0 0x2000
144+
#define ADL_UNC_CTL_THRESHOLD 0x3f000000
145+
#define ADL_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \
146+
SNB_UNC_CTL_UMASK_MASK | \
147+
SNB_UNC_CTL_EDGE_DET | \
148+
SNB_UNC_CTL_INVERT | \
149+
ADL_UNC_CTL_THRESHOLD)
150+
151+
/* ADL ARB register */
152+
#define ADL_UNC_ARB_PER_CTR0 0x2FD2
153+
#define ADL_UNC_ARB_PERFEVTSEL0 0x2FD0
154+
#define ADL_UNC_ARB_MSR_OFFSET 0x8
155+
134156
DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
135157
DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
136158
DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
137159
DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
138160
DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
139161
DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
162+
DEFINE_UNCORE_FORMAT_ATTR(threshold, threshold, "config:24-29");
140163

141164
/* Sandy Bridge uncore support */
142165
static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
@@ -422,6 +445,106 @@ void tgl_uncore_cpu_init(void)
422445
skl_uncore_msr_ops.init_box = rkl_uncore_msr_init_box;
423446
}
424447

448+
static void adl_uncore_msr_init_box(struct intel_uncore_box *box)
449+
{
450+
if (box->pmu->pmu_idx == 0)
451+
wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);
452+
}
453+
454+
static void adl_uncore_msr_enable_box(struct intel_uncore_box *box)
455+
{
456+
wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);
457+
}
458+
459+
static void adl_uncore_msr_disable_box(struct intel_uncore_box *box)
460+
{
461+
if (box->pmu->pmu_idx == 0)
462+
wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, 0);
463+
}
464+
465+
static void adl_uncore_msr_exit_box(struct intel_uncore_box *box)
466+
{
467+
if (box->pmu->pmu_idx == 0)
468+
wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, 0);
469+
}
470+
471+
static struct intel_uncore_ops adl_uncore_msr_ops = {
472+
.init_box = adl_uncore_msr_init_box,
473+
.enable_box = adl_uncore_msr_enable_box,
474+
.disable_box = adl_uncore_msr_disable_box,
475+
.exit_box = adl_uncore_msr_exit_box,
476+
.disable_event = snb_uncore_msr_disable_event,
477+
.enable_event = snb_uncore_msr_enable_event,
478+
.read_counter = uncore_msr_read_counter,
479+
};
480+
481+
static struct attribute *adl_uncore_formats_attr[] = {
482+
&format_attr_event.attr,
483+
&format_attr_umask.attr,
484+
&format_attr_edge.attr,
485+
&format_attr_inv.attr,
486+
&format_attr_threshold.attr,
487+
NULL,
488+
};
489+
490+
static const struct attribute_group adl_uncore_format_group = {
491+
.name = "format",
492+
.attrs = adl_uncore_formats_attr,
493+
};
494+
495+
static struct intel_uncore_type adl_uncore_cbox = {
496+
.name = "cbox",
497+
.num_counters = 2,
498+
.perf_ctr_bits = 44,
499+
.perf_ctr = ADL_UNC_CBO_0_PER_CTR0,
500+
.event_ctl = ADL_UNC_CBO_0_PERFEVTSEL0,
501+
.event_mask = ADL_UNC_RAW_EVENT_MASK,
502+
.msr_offset = ICL_UNC_CBO_MSR_OFFSET,
503+
.ops = &adl_uncore_msr_ops,
504+
.format_group = &adl_uncore_format_group,
505+
};
506+
507+
static struct intel_uncore_type adl_uncore_arb = {
508+
.name = "arb",
509+
.num_counters = 2,
510+
.num_boxes = 2,
511+
.perf_ctr_bits = 44,
512+
.perf_ctr = ADL_UNC_ARB_PER_CTR0,
513+
.event_ctl = ADL_UNC_ARB_PERFEVTSEL0,
514+
.event_mask = SNB_UNC_RAW_EVENT_MASK,
515+
.msr_offset = ADL_UNC_ARB_MSR_OFFSET,
516+
.constraints = snb_uncore_arb_constraints,
517+
.ops = &adl_uncore_msr_ops,
518+
.format_group = &snb_uncore_format_group,
519+
};
520+
521+
static struct intel_uncore_type adl_uncore_clockbox = {
522+
.name = "clock",
523+
.num_counters = 1,
524+
.num_boxes = 1,
525+
.fixed_ctr_bits = 48,
526+
.fixed_ctr = ADL_UNC_FIXED_CTR,
527+
.fixed_ctl = ADL_UNC_FIXED_CTR_CTRL,
528+
.single_fixed = 1,
529+
.event_mask = SNB_UNC_CTL_EV_SEL_MASK,
530+
.format_group = &icl_uncore_clock_format_group,
531+
.ops = &adl_uncore_msr_ops,
532+
.event_descs = icl_uncore_events,
533+
};
534+
535+
static struct intel_uncore_type *adl_msr_uncores[] = {
536+
&adl_uncore_cbox,
537+
&adl_uncore_arb,
538+
&adl_uncore_clockbox,
539+
NULL,
540+
};
541+
542+
void adl_uncore_cpu_init(void)
543+
{
544+
adl_uncore_cbox.num_boxes = icl_get_cbox_num();
545+
uncore_msr_uncores = adl_msr_uncores;
546+
}
547+
425548
enum {
426549
SNB_PCI_UNCORE_IMC,
427550
};
@@ -1203,6 +1326,14 @@ static const struct pci_device_id tgl_uncore_pci_ids[] = {
12031326
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_H_IMC),
12041327
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
12051328
},
1329+
{ /* IMC */
1330+
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_1_IMC),
1331+
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
1332+
},
1333+
{ /* IMC */
1334+
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_2_IMC),
1335+
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
1336+
},
12061337
{ /* end: all zeroes */ }
12071338
};
12081339

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