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Merge branch 'net-lan969x-add-rgmii-support'
Daniel Machon says: ==================== net: lan969x: add RGMII support == Description: This series is the fourth of a multi-part series, that prepares and adds support for the new lan969x switch driver. The upstreaming efforts is split into multiple series (might change a bit as we go along): 1) Prepare the Sparx5 driver for lan969x (merged) 2) Add support for lan969x (same basic features as Sparx5 provides excl. FDMA and VCAP, merged). 3) Add lan969x VCAP functionality (merged). --> 4) Add RGMII support. 5) Add FDMA support. == RGMII support: The lan969x switch device includes two RGMII port interfaces (port 28 and 29) supporting data speeds of 1 Gbps, 100 Mbps and 10 Mbps. == Patch breakdown: Patch #1 does some preparation work. Patch #2 adds new function: is_port_rgmii() to the match data ops. Patch #3 uses the is_port_rgmii() in a number of places. Patch #4 makes sure that we do not configure an RGMII device as a low-speed device, when doing a port config. Patch #5 makes sure we only return the PCS if the port mode requires it. Patch #6 adds checks for RGMII PHY modes in sparx5_verify_speeds(). Patch #7 adds registers required to configure RGMII. Patch #8 adds RGMII implementation. Patch #9 documents RGMII delays in the dt-bindings. Details are in the commit description of the individual patches v4: https://lore.kernel.org/20241213-sparx5-lan969x-switch-driver-4-v4-0-d1a72c9c4714@microchip.com v3: https://lore.kernel.org/20241118-sparx5-lan969x-switch-driver-4-v3-0-3cefee5e7e3a@microchip.com v2: https://lore.kernel.org/20241113-sparx5-lan969x-switch-driver-4-v2-0-0db98ac096d1@microchip.com v1: https://lore.kernel.org/20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com ==================== Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-0-fa8ba5dff732@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2 parents 847cf3b + f0706c0 commit 9268abe

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lines changed

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+484
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lines changed

‎Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -129,6 +129,24 @@ properties:
129129
minimum: 0
130130
maximum: 383
131131

132+
rx-internal-delay-ps:
133+
description:
134+
RGMII Receive Clock Delay defined in pico seconds, used to select
135+
the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
136+
3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
137+
any delay. The Default is no delay.
138+
enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
139+
default: 0
140+
141+
tx-internal-delay-ps:
142+
description:
143+
RGMII Transmit Clock Delay defined in pico seconds, used to select
144+
the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
145+
3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
146+
any delay. The Default is no delay.
147+
enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
148+
default: 0
149+
132150
required:
133151
- reg
134152
- phys

‎drivers/net/ethernet/microchip/sparx5/Makefile‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,8 @@ sparx5-switch-$(CONFIG_LAN969X_SWITCH) += lan969x/lan969x_regs.o \
2020
lan969x/lan969x.o \
2121
lan969x/lan969x_calendar.o \
2222
lan969x/lan969x_vcap_ag_api.o \
23-
lan969x/lan969x_vcap_impl.o
23+
lan969x/lan969x_vcap_impl.o \
24+
lan969x/lan969x_rgmii.o
2425

2526
# Provide include files
2627
ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap

‎drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -90,9 +90,12 @@ static const struct sparx5_main_io_resource lan969x_main_iomap[] = {
9090
{ TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */
9191
{ TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */
9292
{ TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */
93+
{ TARGET_DEVRGMII, 0x30e4000, 1 }, /* 0xe30e4000 */
94+
{ TARGET_DEVRGMII + 1, 0x30e8000, 1 }, /* 0xe30e8000 */
9395
{ TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */
9496
{ TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */
9597
{ TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */
98+
{ TARGET_HSIO_WRAP, 0x3408000, 1 }, /* 0xe3408000 */
9699
};
97100

98101
static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = {
@@ -329,13 +332,15 @@ static const struct sparx5_ops lan969x_ops = {
329332
.is_port_5g = &lan969x_port_is_5g,
330333
.is_port_10g = &lan969x_port_is_10g,
331334
.is_port_25g = &lan969x_port_is_25g,
335+
.is_port_rgmii = &lan969x_port_is_rgmii,
332336
.get_port_dev_index = &lan969x_port_dev_mapping,
333337
.get_port_dev_bit = &lan969x_get_dev_mode_bit,
334338
.get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate,
335339
.get_sdlb_group = &lan969x_get_sdlb_group,
336340
.set_port_mux = &lan969x_port_mux_set,
337341
.ptp_irq_handler = &lan969x_ptp_irq_handler,
338342
.dsm_calendar_calc = &lan969x_dsm_calendar_calc,
343+
.port_config_rgmii = &lan969x_port_config_rgmii,
339344
};
340345

341346
const struct sparx5_match_data lan969x_desc = {

‎drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,17 @@ static inline bool lan969x_port_is_25g(int portno)
5959
return false;
6060
}
6161

62+
static inline bool lan969x_port_is_rgmii(int portno)
63+
{
64+
return portno == 28 || portno == 29;
65+
}
66+
6267
/* lan969x_calendar.c */
6368
int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi,
6469
struct sparx5_calendar_data *data);
70+
71+
/* lan969x_rgmii.c */
72+
int lan969x_port_config_rgmii(struct sparx5_port *port,
73+
struct sparx5_port_config *conf);
74+
6575
#endif

‎drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_rgmii.c‎

Lines changed: 224 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,224 @@
1+
// SPDX-License-Identifier: GPL-2.0+
2+
/* Microchip lan969x Switch driver
3+
*
4+
* Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
5+
*/
6+
7+
#include "lan969x.h"
8+
9+
/* Tx clock selectors */
10+
#define LAN969X_RGMII_TX_CLK_SEL_125MHZ 1 /* 1000Mbps */
11+
#define LAN969X_RGMII_TX_CLK_SEL_25MHZ 2 /* 100Mbps */
12+
#define LAN969X_RGMII_TX_CLK_SEL_2M5MHZ 3 /* 10Mbps */
13+
14+
/* Port speed selectors */
15+
#define LAN969X_RGMII_SPEED_SEL_10 0 /* Select 10Mbps speed */
16+
#define LAN969X_RGMII_SPEED_SEL_100 1 /* Select 100Mbps speed */
17+
#define LAN969X_RGMII_SPEED_SEL_1000 2 /* Select 1000Mbps speed */
18+
19+
/* Clock delay selectors */
20+
#define LAN969X_RGMII_CLK_DELAY_SEL_1_0_NS 2 /* Phase shift 45deg */
21+
#define LAN969X_RGMII_CLK_DELAY_SEL_1_7_NS 3 /* Phase shift 77deg */
22+
#define LAN969X_RGMII_CLK_DELAY_SEL_2_0_NS 4 /* Phase shift 90deg */
23+
#define LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS 5 /* Phase shift 112deg */
24+
#define LAN969X_RGMII_CLK_DELAY_SEL_3_0_NS 6 /* Phase shift 135deg */
25+
#define LAN969X_RGMII_CLK_DELAY_SEL_3_3_NS 7 /* Phase shift 147deg */
26+
27+
#define LAN969X_RGMII_PORT_START_IDX 28 /* Index of the first RGMII port */
28+
#define LAN969X_RGMII_IFG_TX 4 /* TX Inter Frame Gap value */
29+
#define LAN969X_RGMII_IFG_RX1 5 /* RX1 Inter Frame Gap value */
30+
#define LAN969X_RGMII_IFG_RX2 1 /* RX2 Inter Frame Gap value */
31+
32+
#define RGMII_PORT_IDX(port) ((port)->portno - LAN969X_RGMII_PORT_START_IDX)
33+
34+
/* Get the tx clock selector based on the port speed. */
35+
static int lan969x_rgmii_get_clk_sel(int speed)
36+
{
37+
return (speed == SPEED_10 ? LAN969X_RGMII_TX_CLK_SEL_2M5MHZ :
38+
speed == SPEED_100 ? LAN969X_RGMII_TX_CLK_SEL_25MHZ :
39+
LAN969X_RGMII_TX_CLK_SEL_125MHZ);
40+
}
41+
42+
/* Get the port speed selector based on the port speed. */
43+
static int lan969x_rgmii_get_speed_sel(int speed)
44+
{
45+
return (speed == SPEED_10 ? LAN969X_RGMII_SPEED_SEL_10 :
46+
speed == SPEED_100 ? LAN969X_RGMII_SPEED_SEL_100 :
47+
LAN969X_RGMII_SPEED_SEL_1000);
48+
}
49+
50+
/* Get the clock delay selector based on the clock delay in picoseconds. */
51+
static int lan969x_rgmii_get_clk_delay_sel(struct sparx5_port *port,
52+
u32 delay_ps, u32 *clk_delay_sel)
53+
{
54+
switch (delay_ps) {
55+
case 0:
56+
/* Hardware default selector. */
57+
*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS;
58+
break;
59+
case 1000:
60+
*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_1_0_NS;
61+
break;
62+
case 1700:
63+
*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_1_7_NS;
64+
break;
65+
case 2000:
66+
*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_0_NS;
67+
break;
68+
case 2500:
69+
*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS;
70+
break;
71+
case 3000:
72+
*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_3_0_NS;
73+
break;
74+
case 3300:
75+
*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_3_3_NS;
76+
break;
77+
default:
78+
dev_err(port->sparx5->dev, "Invalid RGMII delay: %u", delay_ps);
79+
return -EINVAL;
80+
}
81+
82+
return 0;
83+
}
84+
85+
/* Configure the RGMII tx clock frequency. */
86+
static void lan969x_rgmii_tx_clk_config(struct sparx5_port *port,
87+
struct sparx5_port_config *conf)
88+
{
89+
u32 clk_sel = lan969x_rgmii_get_clk_sel(conf->speed);
90+
u32 idx = RGMII_PORT_IDX(port);
91+
92+
/* Take the RGMII clock domain out of reset and set tx clock
93+
* frequency.
94+
*/
95+
spx5_rmw(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(clk_sel) |
96+
HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_SET(0) |
97+
HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_SET(0),
98+
HSIO_WRAP_RGMII_CFG_TX_CLK_CFG |
99+
HSIO_WRAP_RGMII_CFG_RGMII_TX_RST |
100+
HSIO_WRAP_RGMII_CFG_RGMII_RX_RST,
101+
port->sparx5, HSIO_WRAP_RGMII_CFG(idx));
102+
}
103+
104+
/* Configure the RGMII port device. */
105+
static void lan969x_rgmii_port_device_config(struct sparx5_port *port,
106+
struct sparx5_port_config *conf)
107+
{
108+
u32 dtag, dotag, etype, speed_sel, idx = RGMII_PORT_IDX(port);
109+
110+
speed_sel = lan969x_rgmii_get_speed_sel(conf->speed);
111+
112+
etype = (port->vlan_type == SPX5_VLAN_PORT_TYPE_S_CUSTOM ?
113+
port->custom_etype :
114+
port->vlan_type == SPX5_VLAN_PORT_TYPE_C ?
115+
ETH_P_8021Q : ETH_P_8021AD);
116+
117+
dtag = port->max_vlan_tags == SPX5_PORT_MAX_TAGS_TWO;
118+
dotag = port->max_vlan_tags != SPX5_PORT_MAX_TAGS_NONE;
119+
120+
/* Enable the MAC. */
121+
spx5_wr(DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(1) |
122+
DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(1),
123+
port->sparx5, DEVRGMII_MAC_ENA_CFG(idx));
124+
125+
/* Configure the Inter Frame Gap. */
126+
spx5_wr(DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(LAN969X_RGMII_IFG_TX) |
127+
DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(LAN969X_RGMII_IFG_RX1) |
128+
DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(LAN969X_RGMII_IFG_RX2),
129+
port->sparx5, DEVRGMII_MAC_IFG_CFG(idx));
130+
131+
/* Configure port data rate. */
132+
spx5_wr(DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(speed_sel),
133+
port->sparx5, DEVRGMII_DEV_RST_CTRL(idx));
134+
135+
/* Configure VLAN awareness. */
136+
spx5_wr(DEVRGMII_MAC_TAGS_CFG_TAG_ID_SET(etype) |
137+
DEVRGMII_MAC_TAGS_CFG_PB_ENA_SET(dtag) |
138+
DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(dotag) |
139+
DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(dotag),
140+
port->sparx5,
141+
DEVRGMII_MAC_TAGS_CFG(idx));
142+
}
143+
144+
/* Configure the RGMII delay lines in the MAC.
145+
*
146+
* We use the rx-internal-delay-ps" and "tx-internal-delay-ps" properties to
147+
* configure the rx and tx delays for the MAC. If these properties are missing
148+
* or set to zero, the MAC will not apply any delay.
149+
*
150+
* The PHY side delays are determined by the PHY mode
151+
* (e.g. PHY_INTERFACE_MODE_RGMII_{ID, RXID, TXID}), and ignored by the MAC side
152+
* entirely.
153+
*/
154+
static int lan969x_rgmii_delay_config(struct sparx5_port *port,
155+
struct sparx5_port_config *conf)
156+
{
157+
u32 tx_clk_sel, rx_clk_sel, tx_delay_ps = 0, rx_delay_ps = 0;
158+
u32 idx = RGMII_PORT_IDX(port);
159+
int err;
160+
161+
of_property_read_u32(port->of_node, "rx-internal-delay-ps",
162+
&rx_delay_ps);
163+
164+
of_property_read_u32(port->of_node, "tx-internal-delay-ps",
165+
&tx_delay_ps);
166+
167+
err = lan969x_rgmii_get_clk_delay_sel(port, rx_delay_ps, &rx_clk_sel);
168+
if (err)
169+
return err;
170+
171+
err = lan969x_rgmii_get_clk_delay_sel(port, tx_delay_ps, &tx_clk_sel);
172+
if (err)
173+
return err;
174+
175+
/* Configure rx delay. */
176+
spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) |
177+
HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) |
178+
HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(!!rx_delay_ps) |
179+
HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(rx_clk_sel),
180+
HSIO_WRAP_DLL_CFG_DLL_RST |
181+
HSIO_WRAP_DLL_CFG_DLL_ENA |
182+
HSIO_WRAP_DLL_CFG_DLL_CLK_ENA |
183+
HSIO_WRAP_DLL_CFG_DLL_CLK_SEL,
184+
port->sparx5, HSIO_WRAP_DLL_CFG(idx, 0));
185+
186+
/* Configure tx delay. */
187+
spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) |
188+
HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) |
189+
HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(!!tx_delay_ps) |
190+
HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(tx_clk_sel),
191+
HSIO_WRAP_DLL_CFG_DLL_RST |
192+
HSIO_WRAP_DLL_CFG_DLL_ENA |
193+
HSIO_WRAP_DLL_CFG_DLL_CLK_ENA |
194+
HSIO_WRAP_DLL_CFG_DLL_CLK_SEL,
195+
port->sparx5, HSIO_WRAP_DLL_CFG(idx, 1));
196+
197+
return 0;
198+
}
199+
200+
/* Configure GPIO's to be used as RGMII interface. */
201+
static void lan969x_rgmii_gpio_config(struct sparx5_port *port)
202+
{
203+
u32 idx = RGMII_PORT_IDX(port);
204+
205+
/* Enable the RGMII on the GPIOs. */
206+
spx5_wr(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(1), port->sparx5,
207+
HSIO_WRAP_XMII_CFG(!idx));
208+
}
209+
210+
int lan969x_port_config_rgmii(struct sparx5_port *port,
211+
struct sparx5_port_config *conf)
212+
{
213+
int err;
214+
215+
err = lan969x_rgmii_delay_config(port, conf);
216+
if (err)
217+
return err;
218+
219+
lan969x_rgmii_tx_clk_config(port, conf);
220+
lan969x_rgmii_gpio_config(port);
221+
lan969x_rgmii_port_device_config(port, conf);
222+
223+
return 0;
224+
}

‎drivers/net/ethernet/microchip/sparx5/sparx5_main.c‎

Lines changed: 21 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -313,10 +313,13 @@ static int sparx5_create_port(struct sparx5 *sparx5,
313313
struct initial_port_config *config)
314314
{
315315
struct sparx5_port *spx5_port;
316+
const struct sparx5_ops *ops;
316317
struct net_device *ndev;
317318
struct phylink *phylink;
318319
int err;
319320

321+
ops = sparx5->data->ops;
322+
320323
ndev = sparx5_create_netdev(sparx5, config->portno);
321324
if (IS_ERR(ndev)) {
322325
dev_err(sparx5->dev, "Could not create net device: %02u\n",
@@ -357,6 +360,9 @@ static int sparx5_create_port(struct sparx5 *sparx5,
357360
MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD |
358361
MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD;
359362

363+
if (ops->is_port_rgmii(spx5_port->portno))
364+
phy_interface_set_rgmii(spx5_port->phylink_config.supported_interfaces);
365+
360366
__set_bit(PHY_INTERFACE_MODE_SGMII,
361367
spx5_port->phylink_config.supported_interfaces);
362368
__set_bit(PHY_INTERFACE_MODE_QSGMII,
@@ -830,6 +836,7 @@ static int mchp_sparx5_probe(struct platform_device *pdev)
830836
struct initial_port_config *configs, *config;
831837
struct device_node *np = pdev->dev.of_node;
832838
struct device_node *ports, *portnp;
839+
const struct sparx5_ops *ops;
833840
struct reset_control *reset;
834841
struct sparx5 *sparx5;
835842
int idx = 0, err = 0;
@@ -851,6 +858,7 @@ static int mchp_sparx5_probe(struct platform_device *pdev)
851858
return -EINVAL;
852859

853860
regs = sparx5->data->regs;
861+
ops = sparx5->data->ops;
854862

855863
/* Do switch core reset if available */
856864
reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
@@ -880,7 +888,7 @@ static int mchp_sparx5_probe(struct platform_device *pdev)
880888

881889
for_each_available_child_of_node(ports, portnp) {
882890
struct sparx5_port_config *conf;
883-
struct phy *serdes;
891+
struct phy *serdes = NULL;
884892
u32 portno;
885893

886894
err = of_property_read_u32(portnp, "reg", &portno);
@@ -910,13 +918,17 @@ static int mchp_sparx5_probe(struct platform_device *pdev)
910918
conf->sd_sgpio = ~0;
911919
else
912920
sparx5->sd_sgpio_remapping = true;
913-
serdes = devm_of_phy_get(sparx5->dev, portnp, NULL);
914-
if (IS_ERR(serdes)) {
915-
err = dev_err_probe(sparx5->dev, PTR_ERR(serdes),
916-
"port %u: missing serdes\n",
917-
portno);
918-
of_node_put(portnp);
919-
goto cleanup_config;
921+
/* There is no SerDes node for RGMII ports. */
922+
if (!ops->is_port_rgmii(portno)) {
923+
serdes = devm_of_phy_get(sparx5->dev, portnp, NULL);
924+
if (IS_ERR(serdes)) {
925+
err = dev_err_probe(sparx5->dev,
926+
PTR_ERR(serdes),
927+
"port %u: missing serdes\n",
928+
portno);
929+
of_node_put(portnp);
930+
goto cleanup_config;
931+
}
920932
}
921933
config->portno = portno;
922934
config->node = portnp;
@@ -1072,6 +1084,7 @@ static const struct sparx5_ops sparx5_ops = {
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.is_port_5g = &sparx5_port_is_5g,
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.is_port_10g = &sparx5_port_is_10g,
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.is_port_25g = &sparx5_port_is_25g,
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.is_port_rgmii = &sparx5_port_is_rgmii,
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.get_port_dev_index = &sparx5_port_dev_mapping,
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.get_port_dev_bit = &sparx5_port_dev_mapping,
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.get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate,

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