Skip to content

Commit adb613f

Browse files
prabhakarladgeertu
prabhakarlad
authored and
geertu
committed
pinctrl: renesas: rzg2l: Add support to get/set drive-strength and output-impedance-ohms
RZ/G2L supports two groups of pins Group-A and Group-B. For Group-A pins drive-strength can be configured and for Group-B output-impedance can be configured. This patch splits PIN_CFG_IOLH macro to PIN_CFG_IOLH_A/B and adds support to get/set drive-strength and output-impedance-ohms for the supported pins. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211110224622.16022-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 parent 22972a2 commit adb613f

File tree

1 file changed

+113
-48
lines changed

1 file changed

+113
-48
lines changed

‎drivers/pinctrl/renesas/pinctrl-rzg2l.c‎

Lines changed: 113 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -35,20 +35,21 @@
3535
#define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
3636

3737
/* PIN capabilities */
38-
#define PIN_CFG_IOLH BIT(0)
39-
#define PIN_CFG_SR BIT(1)
40-
#define PIN_CFG_IEN BIT(2)
41-
#define PIN_CFG_PUPD BIT(3)
42-
#define PIN_CFG_IO_VMC_SD0 BIT(4)
43-
#define PIN_CFG_IO_VMC_SD1 BIT(5)
44-
#define PIN_CFG_IO_VMC_QSPI BIT(6)
45-
#define PIN_CFG_IO_VMC_ETH0 BIT(7)
46-
#define PIN_CFG_IO_VMC_ETH1 BIT(8)
47-
#define PIN_CFG_FILONOFF BIT(9)
48-
#define PIN_CFG_FILNUM BIT(10)
49-
#define PIN_CFG_FILCLKSEL BIT(11)
50-
51-
#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH | \
38+
#define PIN_CFG_IOLH_A BIT(0)
39+
#define PIN_CFG_IOLH_B BIT(1)
40+
#define PIN_CFG_SR BIT(2)
41+
#define PIN_CFG_IEN BIT(3)
42+
#define PIN_CFG_PUPD BIT(4)
43+
#define PIN_CFG_IO_VMC_SD0 BIT(5)
44+
#define PIN_CFG_IO_VMC_SD1 BIT(6)
45+
#define PIN_CFG_IO_VMC_QSPI BIT(7)
46+
#define PIN_CFG_IO_VMC_ETH0 BIT(8)
47+
#define PIN_CFG_IO_VMC_ETH1 BIT(9)
48+
#define PIN_CFG_FILONOFF BIT(10)
49+
#define PIN_CFG_FILNUM BIT(11)
50+
#define PIN_CFG_FILCLKSEL BIT(12)
51+
52+
#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \
5253
PIN_CFG_SR | \
5354
PIN_CFG_PUPD | \
5455
PIN_CFG_FILONOFF | \
@@ -86,6 +87,7 @@
8687
#define PMC(n) (0x0200 + 0x10 + (n))
8788
#define PFC(n) (0x0400 + 0x40 + (n) * 4)
8889
#define PIN(n) (0x0800 + 0x10 + (n))
90+
#define IOLH(n) (0x1000 + (n) * 8)
8991
#define IEN(n) (0x1800 + (n) * 8)
9092
#define PWPR (0x3014)
9193
#define SD_CH(n) (0x3000 + (n) * 4)
@@ -101,6 +103,7 @@
101103
#define PVDD_MASK 0x01
102104
#define PFC_MASK 0x07
103105
#define IEN_MASK 0x01
106+
#define IOLH_MASK 0x03
104107

105108
#define PM_INPUT 0x1
106109
#define PM_OUTPUT 0x2
@@ -138,6 +141,9 @@ struct rzg2l_pinctrl {
138141
spinlock_t lock;
139142
};
140143

144+
static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 };
145+
static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 };
146+
141147
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
142148
u8 port, u8 pin, u8 func)
143149
{
@@ -532,6 +538,28 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
532538
break;
533539
}
534540

541+
case PIN_CONFIG_DRIVE_STRENGTH: {
542+
unsigned int index;
543+
544+
if (!(cfg & PIN_CFG_IOLH_A))
545+
return -EINVAL;
546+
547+
index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK);
548+
arg = iolh_groupa_mA[index];
549+
break;
550+
}
551+
552+
case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
553+
unsigned int index;
554+
555+
if (!(cfg & PIN_CFG_IOLH_B))
556+
return -EINVAL;
557+
558+
index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK);
559+
arg = iolh_groupb_oi[index];
560+
break;
561+
}
562+
535563
default:
536564
return -ENOTSUPP;
537565
}
@@ -609,6 +637,43 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
609637
spin_unlock_irqrestore(&pctrl->lock, flags);
610638
break;
611639
}
640+
641+
case PIN_CONFIG_DRIVE_STRENGTH: {
642+
unsigned int arg = pinconf_to_config_argument(_configs[i]);
643+
unsigned int index;
644+
645+
if (!(cfg & PIN_CFG_IOLH_A))
646+
return -EINVAL;
647+
648+
for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) {
649+
if (arg == iolh_groupa_mA[index])
650+
break;
651+
}
652+
if (index >= ARRAY_SIZE(iolh_groupa_mA))
653+
return -EINVAL;
654+
655+
rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index);
656+
break;
657+
}
658+
659+
case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
660+
unsigned int arg = pinconf_to_config_argument(_configs[i]);
661+
unsigned int index;
662+
663+
if (!(cfg & PIN_CFG_IOLH_B))
664+
return -EINVAL;
665+
666+
for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) {
667+
if (arg == iolh_groupb_oi[index])
668+
break;
669+
}
670+
if (index >= ARRAY_SIZE(iolh_groupb_oi))
671+
return -EINVAL;
672+
673+
rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index);
674+
break;
675+
}
676+
612677
default:
613678
return -EOPNOTSUPP;
614679
}
@@ -935,75 +1000,75 @@ static struct rzg2l_dedicated_configs rzg2l_dedicated_pins[] = {
9351000
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
9361001
(PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
9371002
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
938-
(PIN_CFG_SR | PIN_CFG_IOLH | PIN_CFG_IEN)) },
1003+
(PIN_CFG_SR | PIN_CFG_IOLH_A | PIN_CFG_IEN)) },
9391004
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
940-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN)) },
1005+
(PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
9411006
{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
9421007
{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
9431008
{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
944-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
1009+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
9451010
{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
946-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1011+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
9471012
{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
948-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
1013+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
9491014
{ "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
950-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1015+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
9511016
{ "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
952-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1017+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
9531018
{ "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
954-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1019+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
9551020
{ "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
956-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1021+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
9571022
{ "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
958-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1023+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
9591024
{ "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
960-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1025+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
9611026
{ "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
962-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1027+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
9631028
{ "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
964-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1029+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
9651030
{ "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
966-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1))},
1031+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
9671032
{ "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
968-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1033+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
9691034
{ "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
970-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1035+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
9711036
{ "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
972-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1037+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
9731038
{ "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
974-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1039+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
9751040
{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
976-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1041+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
9771042
{ "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
978-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1043+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
9791044
{ "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
980-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1045+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
9811046
{ "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
982-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1047+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
9831048
{ "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
984-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1049+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
9851050
{ "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
986-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1051+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
9871052
{ "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
988-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1053+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
9891054
{ "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
990-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1055+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
9911056
{ "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
992-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1057+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
9931058
{ "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
994-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1059+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
9951060
{ "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
996-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1061+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
9971062
{ "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
998-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1063+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
9991064
{ "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
1000-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1065+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
10011066
{ "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
1002-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1067+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
10031068
{ "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
1004-
(PIN_CFG_IOLH | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1069+
(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
10051070
{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1006-
{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH | PIN_CFG_SR)) },
1071+
{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
10071072
{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
10081073
{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
10091074
{ "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },

0 commit comments

Comments
 (0)