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rodrigovivirodrigovivi
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drm/xe: Introduce the RPa information
RPa is the Achievable frequency, defined by PCODE at runtime based on multiple running conditions. v2: Remove RPA_MASK from i915 file Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241220152936.623627-1-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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‎drivers/gpu/drm/xe/regs/xe_regs.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,12 +44,16 @@
4444

4545
#define MTL_RP_STATE_CAP XE_REG(0x138000)
4646

47+
#define MTL_GT_RPA_FREQUENCY XE_REG(0x138008)
4748
#define MTL_GT_RPE_FREQUENCY XE_REG(0x13800c)
4849

4950
#define MTL_MEDIAP_STATE_CAP XE_REG(0x138020)
5051
#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
5152
#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
5253

54+
#define MTL_MPA_FREQUENCY XE_REG(0x138028)
55+
#define MTL_RPA_MASK REG_GENMASK(8, 0)
56+
5357
#define MTL_MPE_FREQUENCY XE_REG(0x13802c)
5458
#define MTL_RPE_MASK REG_GENMASK(8, 0)
5559

‎drivers/gpu/drm/xe/xe_gt_freq.c‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,20 @@ static ssize_t rpe_freq_show(struct device *dev,
115115
}
116116
static DEVICE_ATTR_RO(rpe_freq);
117117

118+
static ssize_t rpa_freq_show(struct device *dev,
119+
struct device_attribute *attr, char *buf)
120+
{
121+
struct xe_guc_pc *pc = dev_to_pc(dev);
122+
u32 freq;
123+
124+
xe_pm_runtime_get(dev_to_xe(dev));
125+
freq = xe_guc_pc_get_rpa_freq(pc);
126+
xe_pm_runtime_put(dev_to_xe(dev));
127+
128+
return sysfs_emit(buf, "%d\n", freq);
129+
}
130+
static DEVICE_ATTR_RO(rpa_freq);
131+
118132
static ssize_t rpn_freq_show(struct device *dev,
119133
struct device_attribute *attr, char *buf)
120134
{
@@ -202,6 +216,7 @@ static const struct attribute *freq_attrs[] = {
202216
&dev_attr_act_freq.attr,
203217
&dev_attr_cur_freq.attr,
204218
&dev_attr_rp0_freq.attr,
219+
&dev_attr_rpa_freq.attr,
205220
&dev_attr_rpe_freq.attr,
206221
&dev_attr_rpn_freq.attr,
207222
&dev_attr_min_freq.attr,

‎drivers/gpu/drm/xe/xe_guc_pc.c‎

Lines changed: 51 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@
3838

3939
#define FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
4040
#define RPE_MASK REG_GENMASK(15, 8)
41+
#define RPA_MASK REG_GENMASK(31, 16)
4142

4243
#define GT_PERF_STATUS XE_REG(0x1381b4)
4344
#define CAGF_MASK REG_GENMASK(19, 11)
@@ -328,6 +329,19 @@ static int pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
328329
freq);
329330
}
330331

332+
static void mtl_update_rpa_value(struct xe_guc_pc *pc)
333+
{
334+
struct xe_gt *gt = pc_to_gt(pc);
335+
u32 reg;
336+
337+
if (xe_gt_is_media_type(gt))
338+
reg = xe_mmio_read32(&gt->mmio, MTL_MPA_FREQUENCY);
339+
else
340+
reg = xe_mmio_read32(&gt->mmio, MTL_GT_RPA_FREQUENCY);
341+
342+
pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg));
343+
}
344+
331345
static void mtl_update_rpe_value(struct xe_guc_pc *pc)
332346
{
333347
struct xe_gt *gt = pc_to_gt(pc);
@@ -341,6 +355,25 @@ static void mtl_update_rpe_value(struct xe_guc_pc *pc)
341355
pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
342356
}
343357

358+
static void tgl_update_rpa_value(struct xe_guc_pc *pc)
359+
{
360+
struct xe_gt *gt = pc_to_gt(pc);
361+
struct xe_device *xe = gt_to_xe(gt);
362+
u32 reg;
363+
364+
/*
365+
* For PVC we still need to use fused RP1 as the approximation for RPe
366+
* For other platforms than PVC we get the resolved RPe directly from
367+
* PCODE at a different register
368+
*/
369+
if (xe->info.platform == XE_PVC)
370+
reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP);
371+
else
372+
reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC);
373+
374+
pc->rpa_freq = REG_FIELD_GET(RPA_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
375+
}
376+
344377
static void tgl_update_rpe_value(struct xe_guc_pc *pc)
345378
{
346379
struct xe_gt *gt = pc_to_gt(pc);
@@ -365,10 +398,13 @@ static void pc_update_rp_values(struct xe_guc_pc *pc)
365398
struct xe_gt *gt = pc_to_gt(pc);
366399
struct xe_device *xe = gt_to_xe(gt);
367400

368-
if (GRAPHICS_VERx100(xe) >= 1270)
401+
if (GRAPHICS_VERx100(xe) >= 1270) {
402+
mtl_update_rpa_value(pc);
369403
mtl_update_rpe_value(pc);
370-
else
404+
} else {
405+
tgl_update_rpa_value(pc);
371406
tgl_update_rpe_value(pc);
407+
}
372408

373409
/*
374410
* RPe is decided at runtime by PCODE. In the rare case where that's
@@ -447,6 +483,19 @@ u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc)
447483
return pc->rp0_freq;
448484
}
449485

486+
/**
487+
* xe_guc_pc_get_rpa_freq - Get the RPa freq
488+
* @pc: The GuC PC
489+
*
490+
* Returns: RPa freq.
491+
*/
492+
u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc)
493+
{
494+
pc_update_rp_values(pc);
495+
496+
return pc->rpa_freq;
497+
}
498+
450499
/**
451500
* xe_guc_pc_get_rpe_freq - Get the RPe freq
452501
* @pc: The GuC PC

‎drivers/gpu/drm/xe/xe_guc_pc.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc);
2121
u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc);
2222
int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq);
2323
u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc);
24+
u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc);
2425
u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc);
2526
u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc);
2627
int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq);

‎drivers/gpu/drm/xe/xe_guc_pc_types.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,8 @@ struct xe_guc_pc {
1717
struct xe_bo *bo;
1818
/** @rp0_freq: HW RP0 frequency - The Maximum one */
1919
u32 rp0_freq;
20+
/** @rpa_freq: HW RPa frequency - The Achievable one */
21+
u32 rpa_freq;
2022
/** @rpe_freq: HW RPe frequency - The Efficient one */
2123
u32 rpe_freq;
2224
/** @rpn_freq: HW RPN frequency - The Minimum one */

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