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Bo Jiaonbd168
Bo Jiao
authored and
nbd168
committed
mt76: mt7915: refine register definition
Add mt7915_reg_desc to differentiate chip generations. This is an intermediate patch to introduce mt7916 support. Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com> Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com> Co-developed-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Bo Jiao <Bo.Jiao@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
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9 files changed

+947
-409
lines changed

9 files changed

+947
-409
lines changed

‎drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -521,28 +521,28 @@ mt7915_tx_stats_show(struct seq_file *file, void *data)
521521
DEFINE_SHOW_ATTRIBUTE(mt7915_tx_stats);
522522

523523
static void
524-
mt7915_hw_queue_read(struct seq_file *s, u32 base, u32 size,
524+
mt7915_hw_queue_read(struct seq_file *s, u32 size,
525525
const struct hw_queue_map *map)
526526
{
527527
struct mt7915_phy *phy = s->private;
528528
struct mt7915_dev *dev = phy->dev;
529529
u32 i, val;
530530

531-
val = mt76_rr(dev, base + MT_FL_Q_EMPTY);
531+
val = mt76_rr(dev, MT_FL_Q_EMPTY);
532532
for (i = 0; i < size; i++) {
533533
u32 ctrl, head, tail, queued;
534534

535535
if (val & BIT(map[i].index))
536536
continue;
537537

538538
ctrl = BIT(31) | (map[i].pid << 10) | (map[i].qid << 24);
539-
mt76_wr(dev, base + MT_FL_Q0_CTRL, ctrl);
539+
mt76_wr(dev, MT_FL_Q0_CTRL, ctrl);
540540

541-
head = mt76_get_field(dev, base + MT_FL_Q2_CTRL,
541+
head = mt76_get_field(dev, MT_FL_Q2_CTRL,
542542
GENMASK(11, 0));
543-
tail = mt76_get_field(dev, base + MT_FL_Q2_CTRL,
543+
tail = mt76_get_field(dev, MT_FL_Q2_CTRL,
544544
GENMASK(27, 16));
545-
queued = mt76_get_field(dev, base + MT_FL_Q3_CTRL,
545+
queued = mt76_get_field(dev, MT_FL_Q3_CTRL,
546546
GENMASK(11, 0));
547547

548548
seq_printf(s, "\t%s: ", map[i].name);
@@ -570,8 +570,8 @@ mt7915_sta_hw_queue_read(void *data, struct ieee80211_sta *sta)
570570
if (val & BIT(offs))
571571
continue;
572572

573-
mt76_wr(dev, MT_PLE_BASE + MT_FL_Q0_CTRL, ctrl | msta->wcid.idx);
574-
qlen = mt76_get_field(dev, MT_PLE_BASE + MT_FL_Q3_CTRL,
573+
mt76_wr(dev, MT_FL_Q0_CTRL, ctrl | msta->wcid.idx);
574+
qlen = mt76_get_field(dev, MT_FL_Q3_CTRL,
575575
GENMASK(11, 0));
576576
seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n",
577577
sta->addr, msta->wcid.idx,
@@ -633,15 +633,15 @@ mt7915_hw_queues_show(struct seq_file *file, void *data)
633633
val, head, tail);
634634

635635
seq_puts(file, "PLE non-empty queue info:\n");
636-
mt7915_hw_queue_read(file, MT_PLE_BASE, ARRAY_SIZE(ple_queue_map),
636+
mt7915_hw_queue_read(file, ARRAY_SIZE(ple_queue_map),
637637
&ple_queue_map[0]);
638638

639639
/* iterate per-sta ple queue */
640640
ieee80211_iterate_stations_atomic(phy->mt76->hw,
641641
mt7915_sta_hw_queue_read, file);
642642
/* pse queue */
643643
seq_puts(file, "PSE non-empty queue info:\n");
644-
mt7915_hw_queue_read(file, MT_PSE_BASE, ARRAY_SIZE(pse_queue_map),
644+
mt7915_hw_queue_read(file, ARRAY_SIZE(pse_queue_map),
645645
&pse_queue_map[0]);
646646

647647
return 0;

‎drivers/net/wireless/mediatek/mt76/mt7915/dma.c‎

Lines changed: 101 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@
55
#include "../dma.h"
66
#include "mac.h"
77

8-
int mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc)
8+
int mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc, int ring_base)
99
{
1010
int i, err;
1111

12-
err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, MT_TX_RING_BASE);
12+
err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, ring_base);
1313
if (err < 0)
1414
return err;
1515

@@ -40,52 +40,90 @@ static int mt7915_poll_tx(struct napi_struct *napi, int budget)
4040
return 0;
4141
}
4242

43+
static void mt7915_dma_config(struct mt7915_dev *dev)
44+
{
45+
#define Q_CONFIG(q, wfdma, int, id) do { \
46+
if (wfdma) \
47+
dev->wfdma_mask |= (1 << (q)); \
48+
dev->q_int_mask[(q)] = int; \
49+
dev->q_id[(q)] = id; \
50+
} while (0)
51+
52+
#define MCUQ_CONFIG(q, wfdma, int, id) Q_CONFIG(q, (wfdma), (int), (id))
53+
#define RXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__RXQ(q), (wfdma), (int), (id))
54+
#define TXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__TXQ(q), (wfdma), (int), (id))
55+
56+
if (is_mt7915(&dev->mt76)) {
57+
RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, MT7915_RXQ_BAND0);
58+
RXQ_CONFIG(MT_RXQ_MCU, WFDMA1, MT_INT_RX_DONE_WM, MT7915_RXQ_MCU_WM);
59+
RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA1, MT_INT_RX_DONE_WA, MT7915_RXQ_MCU_WA);
60+
RXQ_CONFIG(MT_RXQ_EXT, WFDMA0, MT_INT_RX_DONE_BAND1, MT7915_RXQ_BAND1);
61+
RXQ_CONFIG(MT_RXQ_EXT_WA, WFDMA1, MT_INT_RX_DONE_WA_EXT, MT7915_RXQ_MCU_WA_EXT);
62+
TXQ_CONFIG(0, WFDMA1, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0);
63+
TXQ_CONFIG(1, WFDMA1, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1);
64+
MCUQ_CONFIG(MT_MCUQ_WM, WFDMA1, MT_INT_TX_DONE_MCU_WM, MT7915_TXQ_MCU_WM);
65+
MCUQ_CONFIG(MT_MCUQ_WA, WFDMA1, MT_INT_TX_DONE_MCU_WA, MT7915_TXQ_MCU_WA);
66+
MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA1, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL);
67+
} else {
68+
RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0_MT7916, MT7916_RXQ_BAND0);
69+
RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7916_RXQ_MCU_WM);
70+
RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7916_RXQ_MCU_WA);
71+
RXQ_CONFIG(MT_RXQ_EXT, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916, MT7916_RXQ_BAND1);
72+
RXQ_CONFIG(MT_RXQ_EXT_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT_MT7916, MT7916_RXQ_MCU_WA_EXT);
73+
TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0);
74+
TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1);
75+
MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7915_TXQ_MCU_WM);
76+
MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA_MT7916, MT7915_TXQ_MCU_WA);
77+
MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL);
78+
}
79+
}
80+
4381
static void __mt7915_dma_prefetch(struct mt7915_dev *dev, u32 ofs)
4482
{
45-
#define PREFETCH(base, depth) ((base) << 16 | (depth))
46-
47-
mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL + ofs, PREFETCH(0x0, 0x4));
48-
mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL + ofs, PREFETCH(0x40, 0x4));
49-
mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL + ofs, PREFETCH(0x80, 0x0));
50-
51-
mt76_wr(dev, MT_WFDMA1_TX_RING0_EXT_CTRL + ofs, PREFETCH(0x80, 0x4));
52-
mt76_wr(dev, MT_WFDMA1_TX_RING1_EXT_CTRL + ofs, PREFETCH(0xc0, 0x4));
53-
mt76_wr(dev, MT_WFDMA1_TX_RING2_EXT_CTRL + ofs, PREFETCH(0x100, 0x4));
54-
mt76_wr(dev, MT_WFDMA1_TX_RING3_EXT_CTRL + ofs, PREFETCH(0x140, 0x4));
55-
mt76_wr(dev, MT_WFDMA1_TX_RING4_EXT_CTRL + ofs, PREFETCH(0x180, 0x4));
56-
mt76_wr(dev, MT_WFDMA1_TX_RING5_EXT_CTRL + ofs, PREFETCH(0x1c0, 0x4));
57-
mt76_wr(dev, MT_WFDMA1_TX_RING6_EXT_CTRL + ofs, PREFETCH(0x200, 0x4));
58-
mt76_wr(dev, MT_WFDMA1_TX_RING7_EXT_CTRL + ofs, PREFETCH(0x240, 0x4));
59-
60-
mt76_wr(dev, MT_WFDMA1_TX_RING16_EXT_CTRL + ofs, PREFETCH(0x280, 0x4));
61-
mt76_wr(dev, MT_WFDMA1_TX_RING17_EXT_CTRL + ofs, PREFETCH(0x2c0, 0x4));
62-
mt76_wr(dev, MT_WFDMA1_TX_RING18_EXT_CTRL + ofs, PREFETCH(0x300, 0x4));
63-
mt76_wr(dev, MT_WFDMA1_TX_RING19_EXT_CTRL + ofs, PREFETCH(0x340, 0x4));
64-
mt76_wr(dev, MT_WFDMA1_TX_RING20_EXT_CTRL + ofs, PREFETCH(0x380, 0x4));
65-
mt76_wr(dev, MT_WFDMA1_TX_RING21_EXT_CTRL + ofs, PREFETCH(0x3c0, 0x0));
66-
67-
mt76_wr(dev, MT_WFDMA1_RX_RING0_EXT_CTRL + ofs, PREFETCH(0x3c0, 0x4));
68-
mt76_wr(dev, MT_WFDMA1_RX_RING1_EXT_CTRL + ofs, PREFETCH(0x400, 0x4));
69-
mt76_wr(dev, MT_WFDMA1_RX_RING2_EXT_CTRL + ofs, PREFETCH(0x440, 0x4));
70-
mt76_wr(dev, MT_WFDMA1_RX_RING3_EXT_CTRL + ofs, PREFETCH(0x480, 0x0));
83+
#define PREFETCH(_base, _depth) ((_base) << 16 | (_depth))
84+
85+
/* prefetch SRAM wrapping boundary for tx/rx ring. */
86+
mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x4));
87+
mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x40, 0x4));
88+
mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x80, 0x4));
89+
mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0xc0, 0x4));
90+
mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0x100, 0x4));
91+
92+
mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x140, 0x4));
93+
mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x180, 0x4));
94+
mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_EXT_WA) + ofs, PREFETCH(0x1c0, 0x4));
95+
mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x200, 0x4));
96+
mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_EXT) + ofs, PREFETCH(0x240, 0x4));
97+
98+
/* for mt7915, the ring which is next the last
99+
* used ring must be initialized.
100+
*/
101+
if (is_mt7915(&dev->mt76)) {
102+
ofs += 0x4;
103+
mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0x140, 0x0));
104+
mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_EXT_WA) + ofs, PREFETCH(0x200, 0x0));
105+
mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_EXT) + ofs, PREFETCH(0x280, 0x0));
106+
}
71107
}
72108

73109
void mt7915_dma_prefetch(struct mt7915_dev *dev)
74110
{
75111
__mt7915_dma_prefetch(dev, 0);
76112
if (dev->hif2)
77-
__mt7915_dma_prefetch(dev, MT_WFDMA1_PCIE1_BASE - MT_WFDMA1_BASE);
113+
__mt7915_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0));
78114
}
79115

80116
int mt7915_dma_init(struct mt7915_dev *dev)
81117
{
82118
u32 hif1_ofs = 0;
83119
int ret;
84120

121+
mt7915_dma_config(dev);
122+
85123
mt76_dma_attach(&dev->mt76);
86124

87125
if (dev->hif2)
88-
hif1_ofs = MT_WFDMA1_PCIE1_BASE - MT_WFDMA1_BASE;
126+
hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
89127

90128
/* configure global setting */
91129
mt76_set(dev, MT_WFDMA1_GLO_CFG,
@@ -116,64 +154,79 @@ int mt7915_dma_init(struct mt7915_dev *dev)
116154
mt7915_dma_prefetch(dev);
117155

118156
/* init tx queue */
119-
ret = mt7915_init_tx_queues(&dev->phy, MT7915_TXQ_BAND0,
120-
MT7915_TX_RING_SIZE);
157+
ret = mt7915_init_tx_queues(&dev->phy,
158+
MT_TXQ_ID(0),
159+
MT7915_TX_RING_SIZE,
160+
MT_TXQ_RING_BASE(0));
121161
if (ret)
122162
return ret;
123163

124164
/* command to WM */
125-
ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7915_TXQ_MCU_WM,
126-
MT7915_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
165+
ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM,
166+
MT_MCUQ_ID(MT_MCUQ_WM),
167+
MT7915_TX_MCU_RING_SIZE,
168+
MT_MCUQ_RING_BASE(MT_MCUQ_WM));
127169
if (ret)
128170
return ret;
129171

130172
/* command to WA */
131-
ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA, MT7915_TXQ_MCU_WA,
132-
MT7915_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
173+
ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA,
174+
MT_MCUQ_ID(MT_MCUQ_WA),
175+
MT7915_TX_MCU_RING_SIZE,
176+
MT_MCUQ_RING_BASE(MT_MCUQ_WA));
133177
if (ret)
134178
return ret;
135179

136180
/* firmware download */
137-
ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7915_TXQ_FWDL,
138-
MT7915_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
181+
ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL,
182+
MT_MCUQ_ID(MT_MCUQ_FWDL),
183+
MT7915_TX_FWDL_RING_SIZE,
184+
MT_MCUQ_RING_BASE(MT_MCUQ_FWDL));
139185
if (ret)
140186
return ret;
141187

142188
/* event from WM */
143189
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
144-
MT7915_RXQ_MCU_WM, MT7915_RX_MCU_RING_SIZE,
145-
MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
190+
MT_RXQ_ID(MT_RXQ_MCU),
191+
MT7915_RX_MCU_RING_SIZE,
192+
MT_RX_BUF_SIZE,
193+
MT_RXQ_RING_BASE(MT_RXQ_MCU));
146194
if (ret)
147195
return ret;
148196

149197
/* event from WA */
150198
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
151-
MT7915_RXQ_MCU_WA, MT7915_RX_MCU_RING_SIZE,
152-
MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
199+
MT_RXQ_ID(MT_RXQ_MCU_WA),
200+
MT7915_RX_MCU_RING_SIZE,
201+
MT_RX_BUF_SIZE,
202+
MT_RXQ_RING_BASE(MT_RXQ_MCU_WA));
153203
if (ret)
154204
return ret;
155205

156206
/* rx data queue */
157207
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
158-
MT7915_RXQ_BAND0, MT7915_RX_RING_SIZE,
159-
MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
208+
MT_RXQ_ID(MT_RXQ_MAIN),
209+
MT7915_RX_RING_SIZE,
210+
MT_RX_BUF_SIZE,
211+
MT_RXQ_RING_BASE(MT_RXQ_MAIN));
160212
if (ret)
161213
return ret;
162214

163215
if (dev->dbdc_support) {
164216
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT],
165-
MT7915_RXQ_BAND1, MT7915_RX_RING_SIZE,
217+
MT_RXQ_ID(MT_RXQ_EXT),
218+
MT7915_RX_RING_SIZE,
166219
MT_RX_BUF_SIZE,
167-
MT_RX_DATA_RING_BASE + hif1_ofs);
220+
MT_RXQ_RING_BASE(MT_RXQ_EXT) + hif1_ofs);
168221
if (ret)
169222
return ret;
170223

171224
/* event from WA */
172225
ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT_WA],
173-
MT7915_RXQ_MCU_WA_EXT,
226+
MT_RXQ_ID(MT_RXQ_EXT_WA),
174227
MT7915_RX_MCU_RING_SIZE,
175228
MT_RX_BUF_SIZE,
176-
MT_RX_EVENT_RING_BASE + hif1_ofs);
229+
MT_RXQ_RING_BASE(MT_RXQ_EXT_WA) + hif1_ofs);
177230
if (ret)
178231
return ret;
179232
}

‎drivers/net/wireless/mediatek/mt76/mt7915/init.c‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -461,8 +461,9 @@ static int mt7915_register_ext_phy(struct mt7915_dev *dev)
461461
ETH_ALEN);
462462
mt76_eeprom_override(mphy);
463463

464-
ret = mt7915_init_tx_queues(phy, MT7915_TXQ_BAND1,
465-
MT7915_TX_RING_SIZE);
464+
ret = mt7915_init_tx_queues(phy, MT_TXQ_ID(1),
465+
MT7915_TX_RING_SIZE,
466+
MT_TXQ_RING_BASE(1));
466467
if (ret)
467468
goto error;
468469

@@ -561,7 +562,10 @@ static int mt7915_init_hardware(struct mt7915_dev *dev)
561562
* force firmware operation mode into normal state,
562563
* which should be set before firmware download stage.
563564
*/
564-
mt76_wr(dev, MT_SWDEF_MODE, MT_SWDEF_NORMAL_MODE);
565+
if (is_mt7915(&dev->mt76))
566+
mt76_wr(dev, MT_SWDEF_MODE, MT_SWDEF_NORMAL_MODE);
567+
else
568+
mt76_wr(dev, MT_SWDEF_MODE_MT7916, MT_SWDEF_NORMAL_MODE);
565569

566570
ret = mt7915_mcu_init(dev);
567571
if (ret) {

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