Skip to content

Commit d0f949e

Browse files
Benjamin-GaignardLee Jones
Benjamin-Gaignard
authored and
Lee Jones
committed
mfd: Add STM32 Timers driver
This hardware block could at used at same time for PWM generation and IIO timers. PWM and IIO timer configuration are mixed in the same registers so we need a multi fonction driver to be able to share those registers. version 7: - rebase on v4.10-rc2 version 6: - rename files to stm32-timers - rename functions to stm32_timers_xxx version 5: - fix Lee comments about detect function - add missing dependency on REGMAP_MMIO version 4: - add a function to detect Auto Reload Register (ARR) size - rename the structure shared with other drivers version 2: - rename driver "stm32-gptimer" to be align with SoC documentation - only keep one compatible - use of_platform_populate() instead of devm_mfd_add_devices() Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
1 parent 8f9359c commit d0f949e

File tree

4 files changed

+164
-0
lines changed

4 files changed

+164
-0
lines changed

‎drivers/mfd/Kconfig‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1621,6 +1621,17 @@ config MFD_STW481X
16211621
in various ST Microelectronics and ST-Ericsson embedded
16221622
Nomadik series.
16231623

1624+
config MFD_STM32_TIMERS
1625+
tristate "Support for STM32 Timers"
1626+
depends on (ARCH_STM32 && OF) || COMPILE_TEST
1627+
select MFD_CORE
1628+
select REGMAP
1629+
select REGMAP_MMIO
1630+
help
1631+
Select this option to enable STM32 timers driver used
1632+
for PWM and IIO Timer. This driver allow to share the
1633+
registers between the others drivers.
1634+
16241635
menu "Multimedia Capabilities Port drivers"
16251636
depends on ARCH_SA1100
16261637

‎drivers/mfd/Makefile‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -212,3 +212,5 @@ obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
212212

213213
obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
214214
obj-$(CONFIG_MFD_SUN4I_GPADC) += sun4i-gpadc.o
215+
216+
obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o

‎drivers/mfd/stm32-timers.c‎

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,80 @@
1+
/*
2+
* Copyright (C) STMicroelectronics 2016
3+
*
4+
* Author: Benjamin Gaignard <benjamin.gaignard@st.com>
5+
*
6+
* License terms: GNU General Public License (GPL), version 2
7+
*/
8+
9+
#include <linux/mfd/stm32-timers.h>
10+
#include <linux/module.h>
11+
#include <linux/of_platform.h>
12+
#include <linux/reset.h>
13+
14+
static const struct regmap_config stm32_timers_regmap_cfg = {
15+
.reg_bits = 32,
16+
.val_bits = 32,
17+
.reg_stride = sizeof(u32),
18+
.max_register = 0x400,
19+
};
20+
21+
static void stm32_timers_get_arr_size(struct stm32_timers *ddata)
22+
{
23+
/*
24+
* Only the available bits will be written so when readback
25+
* we get the maximum value of auto reload register
26+
*/
27+
regmap_write(ddata->regmap, TIM_ARR, ~0L);
28+
regmap_read(ddata->regmap, TIM_ARR, &ddata->max_arr);
29+
regmap_write(ddata->regmap, TIM_ARR, 0x0);
30+
}
31+
32+
static int stm32_timers_probe(struct platform_device *pdev)
33+
{
34+
struct device *dev = &pdev->dev;
35+
struct stm32_timers *ddata;
36+
struct resource *res;
37+
void __iomem *mmio;
38+
39+
ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
40+
if (!ddata)
41+
return -ENOMEM;
42+
43+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
44+
mmio = devm_ioremap_resource(dev, res);
45+
if (IS_ERR(mmio))
46+
return PTR_ERR(mmio);
47+
48+
ddata->regmap = devm_regmap_init_mmio_clk(dev, "int", mmio,
49+
&stm32_timers_regmap_cfg);
50+
if (IS_ERR(ddata->regmap))
51+
return PTR_ERR(ddata->regmap);
52+
53+
ddata->clk = devm_clk_get(dev, NULL);
54+
if (IS_ERR(ddata->clk))
55+
return PTR_ERR(ddata->clk);
56+
57+
stm32_timers_get_arr_size(ddata);
58+
59+
platform_set_drvdata(pdev, ddata);
60+
61+
return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
62+
}
63+
64+
static const struct of_device_id stm32_timers_of_match[] = {
65+
{ .compatible = "st,stm32-timers", },
66+
{ /* end node */ },
67+
};
68+
MODULE_DEVICE_TABLE(of, stm32_timers_of_match);
69+
70+
static struct platform_driver stm32_timers_driver = {
71+
.probe = stm32_timers_probe,
72+
.driver = {
73+
.name = "stm32-timers",
74+
.of_match_table = stm32_timers_of_match,
75+
},
76+
};
77+
module_platform_driver(stm32_timers_driver);
78+
79+
MODULE_DESCRIPTION("STMicroelectronics STM32 Timers");
80+
MODULE_LICENSE("GPL v2");

‎include/linux/mfd/stm32-timers.h‎

Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,71 @@
1+
/*
2+
* Copyright (C) STMicroelectronics 2016
3+
*
4+
* Author: Benjamin Gaignard <benjamin.gaignard@st.com>
5+
*
6+
* License terms: GNU General Public License (GPL), version 2
7+
*/
8+
9+
#ifndef _LINUX_STM32_GPTIMER_H_
10+
#define _LINUX_STM32_GPTIMER_H_
11+
12+
#include <linux/clk.h>
13+
#include <linux/regmap.h>
14+
15+
#define TIM_CR1 0x00 /* Control Register 1 */
16+
#define TIM_CR2 0x04 /* Control Register 2 */
17+
#define TIM_SMCR 0x08 /* Slave mode control reg */
18+
#define TIM_DIER 0x0C /* DMA/interrupt register */
19+
#define TIM_SR 0x10 /* Status register */
20+
#define TIM_EGR 0x14 /* Event Generation Reg */
21+
#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
22+
#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
23+
#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
24+
#define TIM_PSC 0x28 /* Prescaler */
25+
#define TIM_ARR 0x2c /* Auto-Reload Register */
26+
#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
27+
#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
28+
#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
29+
#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
30+
#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
31+
32+
#define TIM_CR1_CEN BIT(0) /* Counter Enable */
33+
#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
34+
#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
35+
#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
36+
#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
37+
#define TIM_DIER_UIE BIT(0) /* Update interrupt */
38+
#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
39+
#define TIM_EGR_UG BIT(0) /* Update Generation */
40+
#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
41+
#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
42+
#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
43+
#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
44+
#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
45+
#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
46+
#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
47+
#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
48+
#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
49+
#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
50+
#define TIM_BDTR_BKE BIT(12) /* Break input enable */
51+
#define TIM_BDTR_BKP BIT(13) /* Break input polarity */
52+
#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
53+
#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
54+
#define TIM_BDTR_BKF (BIT(16) | BIT(17) | BIT(18) | BIT(19))
55+
#define TIM_BDTR_BK2F (BIT(20) | BIT(21) | BIT(22) | BIT(23))
56+
#define TIM_BDTR_BK2E BIT(24) /* Break 2 input enable */
57+
#define TIM_BDTR_BK2P BIT(25) /* Break 2 input polarity */
58+
59+
#define MAX_TIM_PSC 0xFFFF
60+
#define TIM_CR2_MMS_SHIFT 4
61+
#define TIM_SMCR_TS_SHIFT 4
62+
#define TIM_BDTR_BKF_MASK 0xF
63+
#define TIM_BDTR_BKF_SHIFT 16
64+
#define TIM_BDTR_BK2F_SHIFT 20
65+
66+
struct stm32_timers {
67+
struct clk *clk;
68+
struct regmap *regmap;
69+
u32 max_arr;
70+
};
71+
#endif

0 commit comments

Comments
 (0)