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Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux
Tariq Toukan says: ==================== mlx5-next updates 2025-01-14 The following pull-request contains mlx5 IFC updates. * 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux: net/mlx5: Add nic_cap_reg and vhca_icm_ctrl registers net/mlx5: SHAMPO: Introduce new SHAMPO specific HCA caps net/mlx5: Add support for MRTCQ register net/mlx5: Update mlx5_ifc to support FEC for 200G per lane link modes ==================== Link: https://patch.msgid.link/20250114055700.1928736-1-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2 parents 9c7ad35 + 6ca00ec commit d90e36f

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lines changed

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+86
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lines changed

‎drivers/net/ethernet/mellanox/mlx5/core/fw.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -281,6 +281,12 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
281281
return err;
282282
}
283283

284+
if (MLX5_CAP_GEN(dev, shampo)) {
285+
err = mlx5_core_get_caps_mode(dev, MLX5_CAP_SHAMPO, HCA_CAP_OPMOD_GET_CUR);
286+
if (err)
287+
return err;
288+
}
289+
284290
return 0;
285291
}
286292

‎drivers/net/ethernet/mellanox/mlx5/core/main.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -368,6 +368,10 @@ int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_ty
368368
u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
369369
int err;
370370

371+
if (WARN_ON(!dev->caps.hca[cap_type]))
372+
/* this cap_type must be added to mlx5_hca_caps_alloc() */
373+
return -EINVAL;
374+
371375
memset(in, 0, sizeof(in));
372376
out = kzalloc(out_sz, GFP_KERNEL);
373377
if (!out)
@@ -1790,6 +1794,7 @@ static const int types[] = {
17901794
MLX5_CAP_MACSEC,
17911795
MLX5_CAP_ADV_VIRTUALIZATION,
17921796
MLX5_CAP_CRYPTO,
1797+
MLX5_CAP_SHAMPO,
17931798
};
17941799

17951800
static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)

‎include/linux/mlx5/device.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1245,6 +1245,7 @@ enum mlx5_cap_type {
12451245
MLX5_CAP_DEV_EVENT = 0x14,
12461246
MLX5_CAP_IPSEC,
12471247
MLX5_CAP_CRYPTO = 0x1a,
1248+
MLX5_CAP_SHAMPO = 0x1d,
12481249
MLX5_CAP_MACSEC = 0x1f,
12491250
MLX5_CAP_GENERAL_2 = 0x20,
12501251
MLX5_CAP_PORT_SELECTION = 0x25,
@@ -1470,6 +1471,9 @@ enum mlx5_qcam_feature_groups {
14701471
#define MLX5_CAP_MACSEC(mdev, cap)\
14711472
MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)
14721473

1474+
#define MLX5_CAP_SHAMPO(mdev, cap) \
1475+
MLX5_GET(shampo_cap, mdev->caps.hca[MLX5_CAP_SHAMPO]->cur, cap)
1476+
14731477
enum {
14741478
MLX5_CMD_STAT_OK = 0x0,
14751479
MLX5_CMD_STAT_INT_ERR = 0x1,

‎include/linux/mlx5/driver.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -160,9 +160,12 @@ enum {
160160
MLX5_REG_MIRC = 0x9162,
161161
MLX5_REG_MTPTM = 0x9180,
162162
MLX5_REG_MTCTR = 0x9181,
163+
MLX5_REG_MRTCQ = 0x9182,
163164
MLX5_REG_SBCAM = 0xB01F,
164165
MLX5_REG_RESOURCE_DUMP = 0xC000,
166+
MLX5_REG_NIC_CAP = 0xC00D,
165167
MLX5_REG_DTOR = 0xC00E,
168+
MLX5_REG_VHCA_ICM_CTRL = 0xC010,
166169
};
167170

168171
enum mlx5_qpts_trust_state {

‎include/linux/mlx5/mlx5_ifc.h‎

Lines changed: 68 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1830,7 +1830,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
18301830
u8 regexp_params[0x1];
18311831
u8 uar_sz[0x6];
18321832
u8 port_selection_cap[0x1];
1833-
u8 reserved_at_251[0x1];
1833+
u8 nic_cap_reg[0x1];
18341834
u8 umem_uid_0[0x1];
18351835
u8 reserved_at_253[0x5];
18361836
u8 log_pg_sz[0x8];
@@ -2329,7 +2329,9 @@ struct mlx5_ifc_wq_bits {
23292329
u8 headers_mkey[0x20];
23302330

23312331
u8 shampo_enable[0x1];
2332-
u8 reserved_at_1e1[0x4];
2332+
u8 reserved_at_1e1[0x1];
2333+
u8 shampo_mode[0x2];
2334+
u8 reserved_at_1e4[0x1];
23332335
u8 log_reservation_size[0x3];
23342336
u8 reserved_at_1e8[0x5];
23352337
u8 log_max_num_of_packets_per_reservation[0x3];
@@ -3327,6 +3329,14 @@ struct mlx5_ifc_dropped_packet_logged_bits {
33273329
u8 reserved_at_0[0xe0];
33283330
};
33293331

3332+
struct mlx5_ifc_nic_cap_reg_bits {
3333+
u8 reserved_at_0[0x1a];
3334+
u8 vhca_icm_ctrl[0x1];
3335+
u8 reserved_at_1b[0x5];
3336+
3337+
u8 reserved_at_20[0x60];
3338+
};
3339+
33303340
struct mlx5_ifc_default_timeout_bits {
33313341
u8 to_multiplier[0x3];
33323342
u8 reserved_at_3[0x9];
@@ -3363,6 +3373,18 @@ struct mlx5_ifc_dtor_reg_bits {
33633373
u8 reserved_at_1c0[0x20];
33643374
};
33653375

3376+
struct mlx5_ifc_vhca_icm_ctrl_reg_bits {
3377+
u8 vhca_id_valid[0x1];
3378+
u8 reserved_at_1[0xf];
3379+
u8 vhca_id[0x10];
3380+
3381+
u8 reserved_at_20[0xa0];
3382+
3383+
u8 cur_alloc_icm[0x20];
3384+
3385+
u8 reserved_at_e0[0x120];
3386+
};
3387+
33663388
enum {
33673389
MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
33683390
MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
@@ -3701,6 +3723,22 @@ struct mlx5_ifc_crypto_cap_bits {
37013723
u8 reserved_at_80[0x780];
37023724
};
37033725

3726+
struct mlx5_ifc_shampo_cap_bits {
3727+
u8 reserved_at_0[0x3];
3728+
u8 shampo_log_max_reservation_size[0x5];
3729+
u8 reserved_at_8[0x3];
3730+
u8 shampo_log_min_reservation_size[0x5];
3731+
u8 shampo_min_mss_size[0x10];
3732+
3733+
u8 shampo_header_split[0x1];
3734+
u8 shampo_header_split_data_merge[0x1];
3735+
u8 reserved_at_22[0x1];
3736+
u8 shampo_log_max_headers_entry_size[0x5];
3737+
u8 reserved_at_28[0x18];
3738+
3739+
u8 reserved_at_40[0x7c0];
3740+
};
3741+
37043742
union mlx5_ifc_hca_cap_union_bits {
37053743
struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
37063744
struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
@@ -10153,7 +10191,21 @@ struct mlx5_ifc_pplm_reg_bits {
1015310191
u8 fec_override_admin_200g_2x[0x10];
1015410192
u8 fec_override_admin_100g_1x[0x10];
1015510193

10156-
u8 reserved_at_260[0x20];
10194+
u8 reserved_at_260[0x60];
10195+
10196+
u8 fec_override_cap_1600g_8x[0x10];
10197+
u8 fec_override_cap_800g_4x[0x10];
10198+
10199+
u8 fec_override_cap_400g_2x[0x10];
10200+
u8 fec_override_cap_200g_1x[0x10];
10201+
10202+
u8 fec_override_admin_1600g_8x[0x10];
10203+
u8 fec_override_admin_800g_4x[0x10];
10204+
10205+
u8 fec_override_admin_400g_2x[0x10];
10206+
u8 fec_override_admin_200g_1x[0x10];
10207+
10208+
u8 reserved_at_340[0x80];
1015710209
};
1015810210

1015910211
struct mlx5_ifc_ppcnt_reg_bits {
@@ -10527,7 +10579,9 @@ struct mlx5_ifc_mtutc_reg_bits {
1052710579
};
1052810580

1052910581
struct mlx5_ifc_pcam_enhanced_features_bits {
10530-
u8 reserved_at_0[0x48];
10582+
u8 reserved_at_0[0x1d];
10583+
u8 fec_200G_per_lane_in_pplm[0x1];
10584+
u8 reserved_at_1e[0x2a];
1053110585
u8 fec_100G_per_lane_in_pplm[0x1];
1053210586
u8 reserved_at_49[0x1f];
1053310587
u8 fec_50G_per_lane_in_pplm[0x1];
@@ -10667,7 +10721,8 @@ struct mlx5_ifc_mcam_access_reg_bits3 {
1066710721

1066810722
u8 regs_63_to_32[0x20];
1066910723

10670-
u8 regs_31_to_2[0x1e];
10724+
u8 regs_31_to_3[0x1d];
10725+
u8 mrtcq[0x1];
1067110726
u8 mtctr[0x1];
1067210727
u8 mtptm[0x1];
1067310728
};
@@ -13158,4 +13213,12 @@ struct mlx5_ifc_msees_reg_bits {
1315813213
u8 reserved_at_80[0x180];
1315913214
};
1316013215

13216+
struct mlx5_ifc_mrtcq_reg_bits {
13217+
u8 reserved_at_0[0x40];
13218+
13219+
u8 rt_clock_identity[0x40];
13220+
13221+
u8 reserved_at_80[0x180];
13222+
};
13223+
1316113224
#endif /* MLX5_IFC_H */

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