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Merge branch 'add-ethtool-sqi-support-for-lan87xx-t1-phy'
Arun Ramadoss says: ==================== add ethtool SQI support for LAN87xx T1 Phy This patch series add the Signal Quality Index measurement for the LAN87xx and LAN937x T1 phy. Updated the maintainers file for microchip_t1.c. ==================== Link: https://lore.kernel.org/r/20220420152016.9680-1-arun.ramadoss@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2 parents 869376d + 58f373f commit e21bebf

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MAINTAINERS

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Original file line numberDiff line numberDiff line change
@@ -12919,6 +12919,13 @@ F: drivers/net/dsa/microchip/*
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F: include/linux/platform_data/microchip-ksz.h
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F: net/dsa/tag_ksz.c
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MICROCHIP LAN87xx/LAN937x T1 PHY DRIVER
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M: Arun Ramadoss <arun.ramadoss@microchip.com>
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R: UNGLinuxDriver@microchip.com
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L: netdev@vger.kernel.org
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S: Maintained
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F: drivers/net/phy/microchip_t1.c
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MICROCHIP LAN743X ETHERNET DRIVER
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M: Bryan Whitehead <bryan.whitehead@microchip.com>
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M: UNGLinuxDriver@microchip.com

drivers/net/phy/microchip_t1.c

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Original file line numberDiff line numberDiff line change
@@ -68,7 +68,12 @@
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#define T1_POST_LCK_MUFACT_CFG_REG 0x1C
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#define T1_TX_RX_FIFO_CFG_REG 0x02
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#define T1_TX_LPF_FIR_CFG_REG 0x55
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#define T1_COEF_CLK_PWR_DN_CFG 0x04
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#define T1_COEF_RW_CTL_CFG 0x0D
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#define T1_SQI_CONFIG_REG 0x2E
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#define T1_SQI_CONFIG2_REG 0x4A
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#define T1_DCQ_SQI_REG 0xC3
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#define T1_DCQ_SQI_MSK GENMASK(3, 1)
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#define T1_MDIO_CONTROL2_REG 0x10
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#define T1_INTERRUPT_SOURCE_REG 0x18
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#define T1_INTERRUPT2_SOURCE_REG 0x08
@@ -82,6 +87,9 @@
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#define T1_MODE_STAT_REG 0x11
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#define T1_LINK_UP_MSK BIT(0)
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/* SQI defines */
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#define LAN87XX_MAX_SQI 0x07
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#define DRIVER_AUTHOR "Nisar Sayed <nisar.sayed@microchip.com>"
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#define DRIVER_DESC "Microchip LAN87XX/LAN937x T1 PHY driver"
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@@ -346,9 +354,20 @@ static int lan87xx_phy_init(struct phy_device *phydev)
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T1_TX_LPF_FIR_CFG_REG, 0x1011, 0 },
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{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
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T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },
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/* Setup SQI measurement */
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{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
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T1_COEF_CLK_PWR_DN_CFG, 0x16d6, 0 },
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/* SQI enable */
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{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
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T1_SQI_CONFIG_REG, 0x9572, 0 },
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/* SQI select mode 5 */
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{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
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T1_SQI_CONFIG2_REG, 0x0001, 0 },
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/* Throws the first SQI reading */
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{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
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T1_COEF_RW_CTL_CFG, 0x0301, 0 },
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{ PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,
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T1_DCQ_SQI_REG, 0, 0 },
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/* Flag LPS and WUR as idle errors */
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{ PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
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T1_MDIO_CONTROL2_REG, 0x0014, 0 },
@@ -724,6 +743,31 @@ static int lan87xx_config_aneg(struct phy_device *phydev)
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return phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
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}
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static int lan87xx_get_sqi(struct phy_device *phydev)
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{
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u8 sqi_value = 0;
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int rc;
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rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
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PHYACC_ATTR_BANK_DSP, T1_COEF_RW_CTL_CFG, 0x0301);
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if (rc < 0)
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return rc;
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rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
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PHYACC_ATTR_BANK_DSP, T1_DCQ_SQI_REG, 0x0);
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if (rc < 0)
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return rc;
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sqi_value = FIELD_GET(T1_DCQ_SQI_MSK, rc);
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return sqi_value;
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}
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static int lan87xx_get_sqi_max(struct phy_device *phydev)
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{
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return LAN87XX_MAX_SQI;
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}
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static struct phy_driver microchip_t1_phy_driver[] = {
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{
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PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX),
@@ -737,6 +781,8 @@ static struct phy_driver microchip_t1_phy_driver[] = {
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.resume = genphy_resume,
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.config_aneg = lan87xx_config_aneg,
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.read_status = lan87xx_read_status,
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.get_sqi = lan87xx_get_sqi,
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.get_sqi_max = lan87xx_get_sqi_max,
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.cable_test_start = lan87xx_cable_test_start,
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.cable_test_get_status = lan87xx_cable_test_get_status,
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},
@@ -750,6 +796,8 @@ static struct phy_driver microchip_t1_phy_driver[] = {
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.resume = genphy_resume,
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.config_aneg = lan87xx_config_aneg,
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.read_status = lan87xx_read_status,
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.get_sqi = lan87xx_get_sqi,
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.get_sqi_max = lan87xx_get_sqi_max,
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.cable_test_start = lan87xx_cable_test_start,
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.cable_test_get_status = lan87xx_cable_test_get_status,
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}

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