diff --git a/file-tests/should-futil/fixed-point-multi-cycle.expect b/file-tests/should-futil/fixed-point-multi-cycle.expect index e0c8e35a..d0445e73 100644 --- a/file-tests/should-futil/fixed-point-multi-cycle.expect +++ b/file-tests/should-futil/fixed-point-multi-cycle.expect @@ -40,8 +40,9 @@ component main() -> () { group upd0<"static"=1> { d0.addr0 = const0.out; d0.write_en = 1'd1; + d0.content_en = 1'd1; d0.write_data = bin_read1_0.out; - upd0[done] = d0.write_done; + upd0[done] = d0.done; } } control { diff --git a/file-tests/should-futil/for-multi-dim.expect b/file-tests/should-futil/for-multi-dim.expect index 42c9ebde..f4cb75ed 100644 --- a/file-tests/should-futil/for-multi-dim.expect +++ b/file-tests/should-futil/for-multi-dim.expect @@ -42,20 +42,22 @@ component main() -> () { } group let2<"static"=2> { A_read0_0.in = A.read_data; - A_read0_0.write_en = A.read_done; + A_read0_0.write_en = A.done; let2[done] = A_read0_0.done; A.addr1 = j0.out; A.addr0 = i0.out; - A.read_en = 1'd1; + A.write_en = 1'd0; + A.content_en = 1'd1; } group upd0<"static"=1> { B.addr1 = j0.out; B.addr0 = i0.out; B.write_en = 1'd1; + B.content_en = 1'd1; add0.left = A_read0_0.out; add0.right = const4.out; B.write_data = add0.out; - upd0[done] = B.write_done; + upd0[done] = B.done; } group upd1<"static"=1> { j0.write_en = 1'd1; diff --git a/file-tests/should-futil/for.expect b/file-tests/should-futil/for.expect index 691ff055..b9a07bc2 100644 --- a/file-tests/should-futil/for.expect +++ b/file-tests/should-futil/for.expect @@ -27,18 +27,20 @@ component main() -> () { } group let1<"static"=2> { A_read0_0.in = A.read_data; - A_read0_0.write_en = A.read_done; + A_read0_0.write_en = A.done; let1[done] = A_read0_0.done; A.addr0 = i0.out; - A.read_en = 1'd1; + A.write_en = 1'd0; + A.content_en = 1'd1; } group upd0<"static"=1> { B.addr0 = i0.out; B.write_en = 1'd1; + B.content_en = 1'd1; add0.left = A_read0_0.out; add0.right = const2.out; B.write_data = add0.out; - upd0[done] = B.write_done; + upd0[done] = B.done; } group upd1<"static"=1> { i0.write_en = 1'd1; diff --git a/file-tests/should-futil/invoke-with-memories.expect b/file-tests/should-futil/invoke-with-memories.expect index af9fe89e..dc4610cd 100644 --- a/file-tests/should-futil/invoke-with-memories.expect +++ b/file-tests/should-futil/invoke-with-memories.expect @@ -17,16 +17,18 @@ component mem_copy() -> () { } group let1<"static"=2> { src_read0_0.in = src.read_data; - src_read0_0.write_en = src.read_done; + src_read0_0.write_en = src.done; let1[done] = src_read0_0.done; src.addr0 = zero_0.out; - src.read_en = 1'd1; + src.write_en = 1'd0; + src.content_en = 1'd1; } group upd0<"static"=1> { dest.addr0 = zero_0.out; dest.write_en = 1'd1; + dest.content_en = 1'd1; dest.write_data = src_read0_0.out; - upd0[done] = dest.write_done; + upd0[done] = dest.done; } } control { diff --git a/file-tests/should-futil/use-plus-equals.expect b/file-tests/should-futil/use-plus-equals.expect index 80302db3..ef5425cb 100644 --- a/file-tests/should-futil/use-plus-equals.expect +++ b/file-tests/should-futil/use-plus-equals.expect @@ -47,20 +47,22 @@ component use_plus_equals() -> () { } group let3<"static"=2> { red_read00.in = x2.read_data; - red_read00.write_en = x2.read_done; + red_read00.write_en = x2.done; let3[done] = red_read00.done; x2.addr1 = __j0.out; x2.addr0 = __i0.out; - x2.read_en = 1'd1; + x2.write_en = 1'd0; + x2.content_en = 1'd1; } group upd0<"static"=1> { x2.addr1 = __j0.out; x2.addr0 = __i0.out; x2.write_en = 1'd1; + x2.content_en = 1'd1; add0.left = red_read00.out; add0.right = __x_0.out; x2.write_data = add0.out; - upd0[done] = x2.write_done; + upd0[done] = x2.done; } group upd1<"static"=1> { __j0.write_en = 1'd1; diff --git a/src/main/scala/backends/calyx/Backend.scala b/src/main/scala/backends/calyx/Backend.scala index 017605b0..17cbfb36 100644 --- a/src/main/scala/backends/calyx/Backend.scala +++ b/src/main/scala/backends/calyx/Backend.scala @@ -644,30 +644,28 @@ private class CalyxBackendHelper { ) ) - val donePortName = - if (rhsInfo.isDefined) "write_done" else "read_done" - // The value is generated on `read_data` and written on `write_data`. val portName = if (rhsInfo.isDefined) "write_data" else "read_data" - // The array ports change if the array is a function parameter. We want to access the // component ports, e.g. `x_read_data`, rather than the memory ports, `x.read_data`. val isParam = (typ == ParameterVar) - val (writeEnPort, donePort, accessPort) = + val (writeEnPort, donePort, accessPort, contentEnPort) = if (isParam) { ( ThisPort(CompVar(s"${id}_write_en")), - ThisPort(CompVar(s"${id}_${donePortName}")), - ThisPort(CompVar(s"${id}_${portName}")) + ThisPort(CompVar(s"${id}_done")), + ThisPort(CompVar(s"${id}_${portName}")), + ThisPort(CompVar(s"${id}_content_en")) ) } else { ( arr.port("write_en"), - arr.port(donePortName), - arr.port(portName) + arr.port("done"), + arr.port(portName), + arr.port("content_en") ) } @@ -683,20 +681,15 @@ private class CalyxBackendHelper { con :: result.structure ++ structs } }) - - val readEnPort = if (isParam) { - ThisPort(CompVar(s"${id}_read_en")) - } else { - arr.port("read_en") - } - // always assign 1 to read_en port if we want to read from seq mem - val readEnStruct = if (rhsInfo.isDefined) List() else List(Assign(ConstantPort(1,1), readEnPort)) + // set ContentEn to 1'd1 + val contentEnStruct = List(Assign(ConstantPort(1,1), contentEnPort)) + // Set write_en to 1'd0 for reads, to port for writes. val writeEnStruct = rhsInfo match { case Some((port, _)) => List(Assign(port, writeEnPort)) - case None => List() + case None => List(Assign(ConstantPort(1,0), writeEnPort)) } val delay = (rhsInfo) match { @@ -707,7 +700,7 @@ private class CalyxBackendHelper { EmitOutput( accessPort, Some(donePort), - (indexing ++ writeEnStruct) ++ readEnStruct, + (indexing ++ writeEnStruct) ++ contentEnStruct, delay, Some((donePort, delay)) )