(c) Copyright 2012-2017 Xilinx, Inc. All Rights Reserved. #----------------------------------------------------------- # Tool version : sds++ 2017.2 SW Build 1972098 on Wed Aug 23 11:35:17 MDT 2017 # Start time : Thu May 02 14:20:10 EDT 2019 # Command line : sds++ -perf-est-hw-only -sds-pf zed -sds-hw test test.cpp -sds-end -clkid 3 -poll-mode 1 -verbose -Wall -O3 -c test.cpp -o test.o # Log file : /home/rn359/git/experiments/_sds/reports/sds_test.log # Journal file : /home/rn359/git/experiments/_sds/reports/sds_test.jou # Report file : /home/rn359/git/experiments/_sds/reports/sds_test.rpt #----------------------------------------------------------- High-Level Synthesis -------------------- Vivado HLS Report : /home/rn359/git/experiments/_sds/vhls/test/solution/syn/report/test_csynth.rpt ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 7.00| 4.37| 1.89| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 37| 37| 38| 38| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: +---------------------+-----------+-----+-----+-----+-----+---------+ | | | Latency | Interval | Pipeline| | Instance | Module | min | max | min | max | Type | +---------------------+-----------+-----+-----+-----+-----+---------+ |grp_add_slice_fu_67 |add_slice | 7| 7| 7| 7| none | +---------------------+-----------+-----+-----+-----+-----+---------+ * Loop: +----------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name| min | max | Latency | achieved | target | Count| Pipelined| +----------+-----+-----+----------+-----------+-----------+------+----------+ |- Loop 1 | 36| 36| 9| -| -| 4| no | +----------+-----+-----+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| -| 0| 21| |FIFO | -| -| -| -| |Instance | -| -| 136| 149| |Memory | -| -| -| -| |Multiplexer | -| -| -| 39| |Register | -| -| 15| -| +-----------------+---------+-------+--------+-------+ |Total | 0| 0| 151| 209| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 0| 0| ~0 | ~0 | +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +---------------------+-----------+---------+-------+-----+-----+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +---------------------+-----------+---------+-------+-----+-----+ |grp_add_slice_fu_67 |add_slice | 0| 0| 136| 149| +---------------------+-----------+---------+-------+-----+-----+ |Total | | 0| 0| 136| 149| +---------------------+-----------+---------+-------+-----+-----+ * DSP48: N/A * Memory: N/A * FIFO: N/A * Expression: +-------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +-------------------+----------+-------+---+----+------------+------------+ |i_1_fu_87_p2 | + | 0| 0| 12| 3| 1| |exitcond_fu_81_p2 | icmp | 0| 0| 9| 3| 4| +-------------------+----------+-------+---+----+------------+------------+ |Total | | 0| 0| 21| 6| 5| +-------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +-----------+----+-----------+-----+-----------+ | Name | LUT| Input Size| Bits| Total Bits| +-----------+----+-----------+-----+-----------+ |ap_NS_fsm | 21| 4| 1| 4| |i_reg_56 | 9| 2| 3| 6| |res_WEN_A | 9| 2| 4| 8| +-----------+----+-----------+-----+-----------+ |Total | 39| 8| 8| 18| +-----------+----+-----------+-----+-----------+ * Register: +-------------------------------------+---+----+-----+-----------+ | Name | FF| LUT| Bits| Const Bits| +-------------------------------------+---+----+-----+-----------+ |ap_CS_fsm | 3| 0| 3| 0| |ap_reg_grp_add_slice_fu_67_ap_start | 1| 0| 1| 0| |i_1_reg_108 | 3| 0| 3| 0| |i_cast1_reg_100 | 3| 0| 32| 29| |i_reg_56 | 3| 0| 3| 0| |tmp_reg_113 | 2| 0| 3| 1| +-------------------------------------+---+----+-----+-----------+ |Total | 15| 0| 45| 30| +-------------------------------------+---+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +------------+-----+-----+------------+--------------+--------------+ |ap_clk | in | 1| ap_ctrl_hs | test | return value | |ap_rst_n | in | 1| ap_ctrl_hs | test | return value | |ap_start | in | 1| ap_ctrl_hs | test | return value | |ap_done | out | 1| ap_ctrl_hs | test | return value | |ap_idle | out | 1| ap_ctrl_hs | test | return value | |ap_ready | out | 1| ap_ctrl_hs | test | return value | |m1_Addr_A | out | 32| bram | m1 | array | |m1_EN_A | out | 1| bram | m1 | array | |m1_WEN_A | out | 4| bram | m1 | array | |m1_Din_A | out | 32| bram | m1 | array | |m1_Dout_A | in | 32| bram | m1 | array | |m1_Clk_A | out | 1| bram | m1 | array | |m1_Rst_A | out | 1| bram | m1 | array | |m2_Addr_A | out | 32| bram | m2 | array | |m2_EN_A | out | 1| bram | m2 | array | |m2_WEN_A | out | 4| bram | m2 | array | |m2_Din_A | out | 32| bram | m2 | array | |m2_Dout_A | in | 32| bram | m2 | array | |m2_Clk_A | out | 1| bram | m2 | array | |m2_Rst_A | out | 1| bram | m2 | array | |res_Addr_A | out | 32| bram | res | array | |res_EN_A | out | 1| bram | res | array | |res_WEN_A | out | 4| bram | res | array | |res_Din_A | out | 32| bram | res | array | |res_Dout_A | in | 32| bram | res | array | |res_Clk_A | out | 1| bram | res | array | |res_Rst_A | out | 1| bram | res | array | +------------+-----+-----+------------+--------------+--------------+