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rvemu-for-book/02/src/cpu.rs

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//! The cpu module contains `Cpu` and implementarion for it.
use crate::bus::*;
use crate::dram::*;
/// The `Cpu` struct that contains registers, a program coutner, system bus that connects
/// peripheral devices, and control and status registers.
pub struct Cpu {
/// 32 64-bit integer registers.
pub regs: [u64; 32],
/// Program counter to hold the the dram address of the next instruction that would be executed.
pub pc: u64,
/// System bus that transfers data between CPU and peripheral devices.
pub bus: Bus,
}
impl Cpu {
/// Create a new `Cpu` object.
pub fn new(binary: Vec<u8>) -> Self {
// The stack pointer (SP) must be set up at first.
let mut regs = [0; 32];
regs[2] = DRAM_BASE + DRAM_SIZE;
Self {
regs,
// The program counter starts from the start address of a dram.
pc: DRAM_BASE,
bus: Bus::new(binary),
}
}
/// Print values in all registers (x0-x31).
pub fn dump_registers(&self) {
let mut output = String::from("");
let abi = [
"zero", " ra ", " sp ", " gp ", " tp ", " t0 ", " t1 ", " t2 ", " s0 ", " s1 ", " a0 ",
" a1 ", " a2 ", " a3 ", " a4 ", " a5 ", " a6 ", " a7 ", " s2 ", " s3 ", " s4 ", " s5 ",
" s6 ", " s7 ", " s8 ", " s9 ", " s10", " s11", " t3 ", " t4 ", " t5 ", " t6 ",
];
for i in (0..32).step_by(4) {
output = format!(
"{}\n{}",
output,
format!(
"x{:02}({})={:>#18x} x{:02}({})={:>#18x} x{:02}({})={:>#18x} x{:02}({})={:>#18x}",
i,
abi[i],
self.regs[i],
i + 1,
abi[i + 1],
self.regs[i + 1],
i + 2,
abi[i + 2],
self.regs[i + 2],
i + 3,
abi[i + 3],
self.regs[i + 3],
)
);
}
println!("{}", output);
}
/// Load a value from a dram.
pub fn load(&mut self, addr: u64, size: u64) -> Result<u64, ()> {
self.bus.load(addr, size)
}
/// Store a value to a dram.
pub fn store(&mut self, addr: u64, size: u64, value: u64) -> Result<(), ()> {
self.bus.store(addr, size, value)
}
/// Get an instruction from the dram.
pub fn fetch(&mut self) -> Result<u64, ()> {
match self.bus.load(self.pc, 32) {
Ok(inst) => Ok(inst),
Err(_e) => Err(()),
}
}
/// Execute an instruction after decoding. Return true if an error happens, otherwise false.
pub fn execute(&mut self, inst: u64) -> Result<(), ()> {
let opcode = inst & 0x7f;
let rd = ((inst >> 7) & 0x1f) as usize;
let rs1 = ((inst >> 15) & 0x1f) as usize;
let rs2 = ((inst >> 20) & 0x1f) as usize;
let funct3 = (inst >> 12) & 0x7;
let funct7 = (inst >> 25) & 0x7f;
// Emulate that register x0 is hardwired with all bits equal to 0.
self.regs[0] = 0;
match opcode {
0x03 => {
// imm[11:0] = inst[31:20]
let imm = ((inst as i32 as i64) >> 20) as u64;
let addr = self.regs[rs1].wrapping_add(imm);
match funct3 {
0x0 => {
// lb
let val = self.load(addr, 8)?;
self.regs[rd] = val as i8 as i64 as u64;
}
0x1 => {
// lh
let val = self.load(addr, 16)?;
self.regs[rd] = val as i16 as i64 as u64;
}
0x2 => {
// lw
let val = self.load(addr, 32)?;
self.regs[rd] = val as i32 as i64 as u64;
}
0x3 => {
// ld
let val = self.load(addr, 64)?;
self.regs[rd] = val;
}
0x4 => {
// lbu
let val = self.load(addr, 8)?;
self.regs[rd] = val;
}
0x5 => {
// lhu
let val = self.load(addr, 16)?;
self.regs[rd] = val;
}
0x6 => {
// lwu
let val = self.load(addr, 32)?;
self.regs[rd] = val;
}
_ => {
println!(
"not implemented yet: opcode {:#x} funct3 {:#x}",
opcode, funct3
);
return Err(());
}
}
}
0x13 => {
// imm[11:0] = inst[31:20]
let imm = ((inst & 0xfff00000) as i32 as i64 >> 20) as u64;
// "The shift amount is encoded in the lower 6 bits of the I-immediate field for RV64I."
let shamt = (imm & 0x3f) as u32;
match funct3 {
0x0 => {
// addi
self.regs[rd] = self.regs[rs1].wrapping_add(imm);
}
0x1 => {
// slli
self.regs[rd] = self.regs[rs1] << shamt;
}
0x2 => {
// slti
self.regs[rd] = if (self.regs[rs1] as i64) < (imm as i64) {
1
} else {
0
};
}
0x3 => {
// sltiu
self.regs[rd] = if self.regs[rs1] < imm { 1 } else { 0 };
}
0x4 => {
// xori
self.regs[rd] = self.regs[rs1] ^ imm;
}
0x5 => {
match funct7 >> 1 {
// srli
0x00 => self.regs[rd] = self.regs[rs1].wrapping_shr(shamt),
// srai
0x10 => {
self.regs[rd] = (self.regs[rs1] as i64).wrapping_shr(shamt) as u64
}
_ => {}
}
}
0x6 => self.regs[rd] = self.regs[rs1] | imm, // ori
0x7 => self.regs[rd] = self.regs[rs1] & imm, // andi
_ => {}
}
}
0x17 => {
// auipc
let imm = (inst & 0xfffff000) as i32 as i64 as u64;
self.regs[rd] = self.pc.wrapping_add(imm).wrapping_sub(4);
}
0x1b => {
let imm = ((inst as i32 as i64) >> 20) as u64;
// "SLLIW, SRLIW, and SRAIW encodings with imm[5] ̸= 0 are reserved."
let shamt = (imm & 0x1f) as u32;
match funct3 {
0x0 => {
// addiw
self.regs[rd] = self.regs[rs1].wrapping_add(imm) as i32 as i64 as u64;
}
0x1 => {
// slliw
self.regs[rd] = self.regs[rs1].wrapping_shl(shamt) as i32 as i64 as u64;
}
0x5 => {
match funct7 {
0x00 => {
// srliw
self.regs[rd] = (self.regs[rs1] as u32).wrapping_shr(shamt) as i32
as i64 as u64;
}
0x20 => {
// sraiw
self.regs[rd] =
(self.regs[rs1] as i32).wrapping_shr(shamt) as i64 as u64;
}
_ => {
println!(
"not implemented yet: opcode {:#x} funct7 {:#x}",
opcode, funct7
);
return Err(());
}
}
}
_ => {
println!(
"not implemented yet: opcode {:#x} funct3 {:#x}",
opcode, funct3
);
return Err(());
}
}
}
0x23 => {
// imm[11:5|4:0] = inst[31:25|11:7]
let imm = (((inst & 0xfe000000) as i32 as i64 >> 20) as u64) | ((inst >> 7) & 0x1f);
let addr = self.regs[rs1].wrapping_add(imm);
match funct3 {
0x0 => self.store(addr, 8, self.regs[rs2])?, // sb
0x1 => self.store(addr, 16, self.regs[rs2])?, // sh
0x2 => self.store(addr, 32, self.regs[rs2])?, // sw
0x3 => self.store(addr, 64, self.regs[rs2])?, // sd
_ => {}
}
}
0x33 => {
// "SLL, SRL, and SRA perform logical left, logical right, and arithmetic right
// shifts on the value in register rs1 by the shift amount held in register rs2.
// In RV64I, only the low 6 bits of rs2 are considered for the shift amount."
let shamt = ((self.regs[rs2] & 0x3f) as u64) as u32;
match (funct3, funct7) {
(0x0, 0x00) => {
// add
self.regs[rd] = self.regs[rs1].wrapping_add(self.regs[rs2]);
}
(0x0, 0x01) => {
// mul
self.regs[rd] = self.regs[rs1].wrapping_mul(self.regs[rs2]);
}
(0x0, 0x20) => {
// sub
self.regs[rd] = self.regs[rs1].wrapping_sub(self.regs[rs2]);
}
(0x1, 0x00) => {
// sll
self.regs[rd] = self.regs[rs1].wrapping_shl(shamt);
}
(0x2, 0x00) => {
// slt
self.regs[rd] = if (self.regs[rs1] as i64) < (self.regs[rs2] as i64) {
1
} else {
0
};
}
(0x3, 0x00) => {
// sltu
self.regs[rd] = if self.regs[rs1] < self.regs[rs2] {
1
} else {
0
};
}
(0x4, 0x00) => {
// xor
self.regs[rd] = self.regs[rs1] ^ self.regs[rs2];
}
(0x5, 0x00) => {
// srl
self.regs[rd] = self.regs[rs1].wrapping_shr(shamt);
}
(0x5, 0x20) => {
// sra
self.regs[rd] = (self.regs[rs1] as i64).wrapping_shr(shamt) as u64;
}
(0x6, 0x00) => {
// or
self.regs[rd] = self.regs[rs1] | self.regs[rs2];
}
(0x7, 0x00) => {
// and
self.regs[rd] = self.regs[rs1] & self.regs[rs2];
}
_ => {
println!(
"not implemented yet: opcode {:#x} funct3 {:#x} funct7 {:#x}",
opcode, funct3, funct7
);
return Err(());
}
}
}
0x37 => {
// lui
self.regs[rd] = (inst & 0xfffff000) as i32 as i64 as u64;
}
0x3b => {
// "The shift amount is given by rs2[4:0]."
let shamt = (self.regs[rs2] & 0x1f) as u32;
match (funct3, funct7) {
(0x0, 0x00) => {
// addw
self.regs[rd] =
self.regs[rs1].wrapping_add(self.regs[rs2]) as i32 as i64 as u64;
}
(0x0, 0x20) => {
// subw
self.regs[rd] =
((self.regs[rs1].wrapping_sub(self.regs[rs2])) as i32) as u64;
}
(0x1, 0x00) => {
// sllw
self.regs[rd] = (self.regs[rs1] as u32).wrapping_shl(shamt) as i32 as u64;
}
(0x5, 0x00) => {
// srlw
self.regs[rd] = (self.regs[rs1] as u32).wrapping_shr(shamt) as i32 as u64;
}
(0x5, 0x20) => {
// sraw
self.regs[rd] = ((self.regs[rs1] as i32) >> (shamt as i32)) as u64;
}
_ => {
println!(
"not implemented yet: opcode {:#x} funct3 {:#x} funct7 {:#x}",
opcode, funct3, funct7
);
return Err(());
}
}
}
0x63 => {
// imm[12|10:5|4:1|11] = inst[31|30:25|11:8|7]
let imm = (((inst & 0x80000000) as i32 as i64 >> 19) as u64)
| ((inst & 0x80) << 4) // imm[11]
| ((inst >> 20) & 0x7e0) // imm[10:5]
| ((inst >> 7) & 0x1e); // imm[4:1]
match funct3 {
0x0 => {
// beq
if self.regs[rs1] == self.regs[rs2] {
self.pc = self.pc.wrapping_add(imm).wrapping_sub(4);
}
}
0x1 => {
// bne
if self.regs[rs1] != self.regs[rs2] {
self.pc = self.pc.wrapping_add(imm).wrapping_sub(4);
}
}
0x4 => {
// blt
if (self.regs[rs1] as i64) < (self.regs[rs2] as i64) {
self.pc = self.pc.wrapping_add(imm).wrapping_sub(4);
}
}
0x5 => {
// bge
if (self.regs[rs1] as i64) >= (self.regs[rs2] as i64) {
self.pc = self.pc.wrapping_add(imm).wrapping_sub(4);
}
}
0x6 => {
// bltu
if self.regs[rs1] < self.regs[rs2] {
self.pc = self.pc.wrapping_add(imm).wrapping_sub(4);
}
}
0x7 => {
// bgeu
if self.regs[rs1] >= self.regs[rs2] {
self.pc = self.pc.wrapping_add(imm).wrapping_sub(4);
}
}
_ => {
println!(
"not implemented yet: opcode {:#x} funct3 {:#x}",
opcode, funct3
);
return Err(());
}
}
}
0x67 => {
// jalr
// Note: Don't add 4 because the pc already moved on.
let t = self.pc;
let imm = ((((inst & 0xfff00000) as i32) as i64) >> 20) as u64;
self.pc = (self.regs[rs1].wrapping_add(imm)) & !1;
self.regs[rd] = t;
}
0x6f => {
// jal
self.regs[rd] = self.pc;
// imm[20|10:1|11|19:12] = inst[31|30:21|20|19:12]
let imm = (((inst & 0x80000000) as i32 as i64 >> 11) as u64) // imm[20]
| (inst & 0xff000) // imm[19:12]
| ((inst >> 9) & 0x800) // imm[11]
| ((inst >> 20) & 0x7fe); // imm[10:1]
self.pc = self.pc.wrapping_add(imm).wrapping_sub(4);
}
_ => {
dbg!(format!("not implemented yet: opcode {:#x}", opcode));
return Err(());
}
}
return Ok(());
}
}