Fix smartreflex for OMAP3621 and add overclocking

dalingrin · May 12, 2011 · aa015b1 · aa015b1
1 parent cecb103
commit aa015b1
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Showing 4 changed files with 66 additions and 4 deletions.
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
@@ -175,6 +175,29 @@ config MACH_OMAP3621_EVT1A
 	depends on ARCH_OMAP3 && ARCH_OMAP34XX
 	select ARCH_OMAP3621
 
+choice
+    bool "Encore clock speed"
+    default ENCORE_MPU_STOCK
+    depends on MACH_OMAP3621_EVT1A
+
+config ENCORE_MPU_STOCK
+    bool "Stock clock speed for OMAP3621"
+    depends on MACH_OMAP3621_EVT1A
+
+config ENCORE_MPU_925MHZ
+    bool "Overclock MPU up to 925mhz"
+    depends on MACH_OMAP3621_EVT1A
+
+config ENCORE_MPU_1100MHZ
+    bool "Overclock MPU up to 1100mhz"
+    depends on MACH_OMAP3621_EVT1A
+
+config ENCORE_MPU_1200MHZ
+    bool "Overclock MPU up to 1200mhz"
+    depends on MACH_OMAP3621_EVT1A
+
+endchoice
+
 config WLAN_POWER_EVT1
 	bool "WLAN power support"
 	depends on MACH_OMAP3621_EVT1A

diff --git a/arch/arm/mach-omap2/omap3-opp.h b/arch/arm/mach-omap2/omap3-opp.h
@@ -5,6 +5,7 @@
 
 /* MPU speeds */
 #define S1200M	1200000000
+#define S1100M  1100000000
 #define S1000M	1000000000
 #define S925M   925000000
 #define S800M	800000000
@@ -41,11 +42,27 @@ static struct omap_opp omap3630_mpu_rate_table[] = {
 	{S600M, VDD1_OPP2, 0x2D, 0x0, 0x0, 0x0},
 	/*OPP3 (OPP130) - 1.26V*/
 	{S800M, VDD1_OPP3, 0x38, 0x0, 0x0, 0x0},
+#ifdef CONFIG_ENCORE_MPU_925MHZ    
 	/*OPP4 (OPP-1G) - 1.35V*/
 	{S925M, VDD1_OPP4, 0x38, 0x0, 0x0, 0x0},
 	/*OPP5 (OPP-1.3G) - 1.38V*/
 	{S1200M, VDD1_OPP5, 0x3E, 0x0, 0x0, 0x0},
-
+#elif CONFIG_ENCORE_MPU_1100MHZ
+	/*OPP4 (OPP-1G) - 1.35V*/
+	{S1000M, VDD1_OPP4, 0x3d, 0x0, 0x0, 0x0},
+	/*OPP5 (OPP-1.3G) - 1.38V*/
+	{S1100M, VDD1_OPP5, 0x3c, 0x0, 0x0, 0x0},
+#elif CONFIG_ENCORE_MPU_1200MHZ
+	/*OPP4 (OPP-1G) - 1.35V*/
+	{S1100M, VDD1_OPP4, 0x3d, 0x0, 0x0, 0x0},
+	/*OPP5 (OPP-1.3G) - 1.38V*/
+	{S1200M, VDD1_OPP5, 0x3e, 0x0, 0x0, 0x0},
+#else
+	/*OPP4 (OPP-1G) - 1.35V*/
+	{S1000M, VDD1_OPP4, 0x38, 0x0, 0x0, 0x0},
+	/*OPP5 (OPP-1.3G) - 1.38V*/
+	{S1200M, VDD1_OPP5, 0x3E, 0x0, 0x0, 0x0},
+#endif
 };
 
 static struct omap_opp omap3630_l3_rate_table[] = {

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
@@ -365,11 +365,19 @@ static void sr_set_testing_nvalues(struct omap_sr *sr)
 			sr->senn_mod = 0x1;
 
 			/* calculate nvalues for each opp */
+#ifndef CONFIG_MACH_OMAP3621_EVT1A
 			sr->opp1_nvalue = cal_test_nvalue(581, 489);
 			sr->opp2_nvalue = cal_test_nvalue(1072, 910);
 			sr->opp3_nvalue = cal_test_nvalue(1405, 1200);
+#endif
+#ifdef CONFIG_ENCORE_MPU_1200MHZ
+			sr->opp4_nvalue = cal_test_nvalue(1842, 1580);
+			sr->opp5_nvalue = cal_test_nvalue(1950, 1680);
+#else
 			sr->opp4_nvalue = cal_test_nvalue(1842, 1580);
 			sr->opp5_nvalue = cal_test_nvalue(1842, 1580);
+#endif
+
 
 			if (sr_margin_steps || sr_margin_steps_1g)
 				sr_add_margin_steps(sr);
@@ -438,15 +446,18 @@ static void sr_set_efuse_nvalues(struct omap_sr *sr)
 				pr_info("SR1:Fused Nvalues for VDD1OPP4 %x\n",
 							sr->opp4_nvalue);
 			} else {
+#ifndef CONFIG_MACH_OMAP3621_EVT1A 
+                pr_info("SR1:Using testing Nvalues\n");
 				/* use test nvalues */
 				sr_set_testing_nvalues(sr);
 				return;
+#endif
 			}
 
 			sr->opp3_nvalue = sr1_opp[3] =
 			   omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP3_VDD1);
 			if (sr->opp3_nvalue != 0) {
-				pr_info("SR2:Fused Nvalues for VDD2OPP3 %d\n",
+				pr_info("SR1:Fused Nvalues for VDD1OPP3 %d\n",
 							sr->opp3_nvalue);
 			} else {
 				/* use test nvalues */
@@ -456,7 +467,7 @@ static void sr_set_efuse_nvalues(struct omap_sr *sr)
 			sr->opp2_nvalue = sr1_opp[2] =
 			   omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP2_VDD1);
 			if (sr->opp2_nvalue != 0) {
-				pr_info("SR2:Fused Nvalues for VDD2OPP2 %d\n",
+				pr_info("SR1:Fused Nvalues for VDD1OPP2 %d\n",
 							sr->opp2_nvalue);
 			} else {
 				/* use test nvalues */
@@ -466,13 +477,18 @@ static void sr_set_efuse_nvalues(struct omap_sr *sr)
 			sr->opp1_nvalue = sr1_opp[1] =
 			   omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP1_VDD1);
 			if (sr->opp1_nvalue != 0) {
-				pr_info("SR2:Fused Nvalues for VDD2OPP1 %d\n",
+				pr_info("SR1:Fused Nvalues for VDD1OPP1 %d\n",
 							sr->opp1_nvalue);
 			} else {
 				/* use test nvalues */
 				sr_set_testing_nvalues(sr);
 				return;
 			}
+#ifdef CONFIG_ENCORE_MPU_1100MHZ || CONFIG_ENCORE_MPU_1200MHZ
+            pr_info("SR1:Adding extra nvalues for OPP4 and OPP5\n");
+            sr_set_testing_nvalues(sr);
+            return;
+#endif
 
 			if (sr_margin_steps || sr_margin_steps_1g)
 				sr_add_margin_steps(sr);

diff --git a/arch/arm/plat-omap/omap-pm-srf.c b/arch/arm/plat-omap/omap-pm-srf.c
@@ -386,7 +386,13 @@ u8 omap_pm_get_max_vdd1_opp()
 	if (cpu_is_omap3622() && has_1GHz_support()) {
 		return VDD1_OPP4;
 	} else if (cpu_is_omap3621()) {
+#ifdef CONFIG_ENCORE_MPU_925MHZ
 		return VDD1_OPP4;
+#elif CONFIG_ENCORE_MPU_1100MHZ || CONFIG_ENCORE_MPU_1200MHZ
+        return VDD1_OPP5;
+#else
+        return VDD1_OPP3;
+#endif
 	} else if (cpu_is_omap3630()) {
 		/*
 		 * Check if VDD1 OPP5 has the right fused value, if 0