Skip to content
master
Go to file
Code

Latest commit

Signed-off-by: David Shah <dave@ds0.me>
582f870

Git stats

Files

Permalink
Failed to load latest commit information.
Type
Name
Latest commit message
Commit time
 
 
 
 
 
 
 
 

README.md

MIPI CSI-2 IP Cores

The vhdl_rx folder contains a tried-and-tested high performance CSI-2 receiver core in VHDL. This can handle 4k video at over 30fps (most likely 60fps with a suitable camera module). This has been tested with the OV13850 camera module with a Xilinx Kintex-7 FPGA. It is currently limited to a 4-lane and 10bpp without modification, other parameters such as timing can be modified at compile time. Also in this folder are an example project and some miscellaneous VHDL support IP such as an AXI-4 framebuffer controller.

The verilog_cores contains work-in-progress CSI-2 transmit and receive cores in Verilog. These are designed to be more flexible and run on a variety of platforms. The first target will be 640x480 video using a Raspberry Pi camera with an iCE40 FPGA.

All cores are licensed under the MIT License, see LICENSE for details.

About

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

Resources

License

Releases

No releases published
You can’t perform that action at this time.