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VHDL Verilog Tcl Shell SystemVerilog Batchfile
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doc initial upload Jul 21, 2019
release
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sys initial upload Jul 21, 2019
ORIC.ipregen.rpt initial upload Jul 21, 2019
ORIC.qpf initial upload Jul 21, 2019
ORIC.qsf initial upload Jul 21, 2019
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ORIC.sv initial upload Jul 21, 2019
ORIC.sv.bak initial upload Jul 21, 2019
RAMB16_S18_S18.cmp initial upload Jul 21, 2019
RAMB16_S18_S18.qip initial upload Jul 21, 2019
RAMB16_S18_S18.vhd initial upload Jul 21, 2019
Readme.txt initial upload Jul 21, 2019
build_id.v initial upload Jul 21, 2019
c5_pin_model_dump.txt initial upload Jul 21, 2019
clean.bat initial upload Jul 21, 2019
jtag.cdf initial upload Jul 21, 2019
pll.xml initial upload Jul 21, 2019
pll_hdmi.xml initial upload Jul 21, 2019
pll_hdmi_cfg.xml initial upload Jul 21, 2019
ram48k.cmp initial upload Jul 21, 2019
ram48k.qip initial upload Jul 21, 2019
ram48k.vhd initial upload Jul 21, 2019

Readme.txt

This is a port of the Oric1 / Atmos.
It is a basic port with no bells or whistles.
It has at present no means of loading programs,
so what you see is what you get.

The framework needs updating to latest release -- fix me



Dave Wood (oldgit)
														




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