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library IEEE;
use IEEE.std_logic_1164.all;
entity fft_core is
port (
ce_1: in std_logic;
clk_1: in std_logic;
pol0: in std_logic_vector(17 downto 0);
pol1: in std_logic_vector(17 downto 0);
pol2: in std_logic_vector(17 downto 0);
pol3: in std_logic_vector(17 downto 0);
shift: in std_logic_vector(15 downto 0);
sync: in std_logic;
oflow: out std_logic;
pol02_out: out std_logic_vector(35 downto 0);
pol13_out: out std_logic_vector(35 downto 0);
sync_out: out std_logic
);
end fft_core;
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