A verilog parser for multi-level combinational logic circuits
What is it?
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This tool is A verilog parser for multi-level combinational logic circuits
How to compile the program?
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Enter the directory verilog-parser
Run the 'make' command
How to run the program?
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Usage: ./verilog-parser <verilog_file.v>
verilog-parser: the executable file
filename.v: the verilog file to parse
* A sample verilog files is located in the directory 'verilog'
For further information, contact:
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David Kebo Houngninou
dhoungninou@smu.edu