A verilog parser for multi-level combinational logic circuits

  What is it?
  -----------
  This tool is A verilog parser for multi-level combinational logic circuits
  
  
  How to compile the program?
  ------------------
  Enter the directory verilog-parser
  Run the 'make' command
  
  
  How to run the program?
  ------------------
  Usage: ./verilog-parser <verilog_file.v>
  verilog-parser: the executable file
  filename.v: the verilog file to parse

  * A sample verilog files is located in the directory 'verilog'

  
  For further information, contact:
  --------
	David Kebo Houngninou
	dhoungninou@smu.edu