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- The wave renderer has been moved to a channel entity.

- We can now control the frequency of the waveform by providing a MIDI compatible pitch value.
- Note: In this version, only the square wave is at the correct frequency.
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1 parent e8fed43 commit 3d7df24ed29c17a38177095e7d147a9578c7c65b unknown committed May 15, 2011
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@@ -1 +1,2 @@
mdsynth.runs
+mdsynth.sim
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@@ -12,6 +12,12 @@ Description
In its current state, the project is a simple wave generator using a sigma-delta DAC. The ouput pin of the DAC is either AA21 or AB21. You will need a RC filter at the output. Refer to the Xilinx application note 154 for more details about the DAC.
+In this version, we have a single voice with a single channel per voice. Each voice has a pitch control and a waveform selection. The same channel is connected to both the left and right audio outputs.
+
+In this example, the pitch requested from the channel is increasing over time from 0 to 127.
+
+The projet has been converted to Xilinx PlanAhead 13.1.
+
Waveform selection
------------------
@@ -22,4 +28,13 @@ SW0 SW1 Waveform
1 0 Sawtooth
1 1 Sine
-Note: In this preliminary version, the frequency is fixed.
+Pitch
+-----
+
+The pitch is MIDI compatible. The value is between 0 and 127, 69 being A4 at 440Hz.
+
+Limitations
+-----------
+
+Only the square wave will be at correct pitch in this version. The other waveforms will require a higher frequency from the pitch to clock converter.
+
Binary file not shown.
@@ -1,14 +1,14 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="6">
- <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc3s700afg484-4" ConstrsSet="constrs_1" State="current" Dir="$PRUNDIR/synth_1" LaunchTime="1302902820">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc3s700afg484-4" ConstrsSet="constrs_1" State="current" Dir="$PRUNDIR/synth_1" LaunchTime="1305485373">
<File Type="PA-XST" Name="mdsynth.xst"/>
<File Type="RUN-SRCS" Name="$PDATADIR/runs/synth_1/sources.xml"/>
<File Type="XST-NGC" Name="mdsynth.ngc"/>
<File Type="PA-XSTPRJ" Name="mdsynth.prj"/>
<File Type="RUN-CONSTRS" Name="$PDATADIR/runs/synth_1/constrs_in.xml"/>
<File Type="XST-SRP" Name="mdsynth.srp"/>
</Run>
- <Run Id="impl_1" Type="Ft2:EntireDesign" SynthRun="synth_1" Part="xc3s700afg484-4" ConstrsSet="constrs_1" State="current" Dir="$PRUNDIR/impl_1" LaunchTime="1302902875">
+ <Run Id="impl_1" Type="Ft2:EntireDesign" SynthRun="synth_1" Part="xc3s700afg484-4" ConstrsSet="constrs_1" State="current" Dir="$PRUNDIR/impl_1" LaunchTime="1305485391">
<File Type="PA-EDIF" Name="mdsynth.edf"/>
<File Type="PAR-PAD" Name="mdsynth_routed_pad.txt"/>
<File Type="PA-UCF" Name="mdsynth.ucf"/>
@@ -20,18 +20,16 @@
<Attr Name="ImportTime" Val="1299885873"/>
</FileInfo>
</File>
- <File Path="$PSRCDIR/sources_1/imports/src/player.vhd">
- <FileInfo>
- <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/player.vhd"/>
- <Attr Name="ImportTime" Val="1299777942"/>
- </FileInfo>
- </File>
<File Path="$PSRCDIR/sources_1/imports/src/sinewave.vhd">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/sinewave.vhd"/>
<Attr Name="ImportTime" Val="1299797437"/>
</FileInfo>
</File>
+ <File Path="$PSRCDIR/sources_1/new/pitch_clk_div.vhd">
+ </File>
+ <File Path="$PSRCDIR/sources_1/imports/src/channel.vhd">
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="mdsynth"/>
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<DARoots Version="1" Minor="12">
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="mdsynth"/>
+ <Option Name="SimMode" Val="timing"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+</DARoots>
+
@@ -20,18 +20,16 @@
<Attr Name="ImportTime" Val="1299885873"/>
</FileInfo>
</File>
- <File Path="$PSRCDIR/sources_1/imports/src/player.vhd">
- <FileInfo>
- <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/player.vhd"/>
- <Attr Name="ImportTime" Val="1299777942"/>
- </FileInfo>
- </File>
<File Path="$PSRCDIR/sources_1/imports/src/sinewave.vhd">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/sinewave.vhd"/>
<Attr Name="ImportTime" Val="1299797437"/>
</FileInfo>
</File>
+ <File Path="$PSRCDIR/sources_1/new/pitch_clk_div.vhd">
+ </File>
+ <File Path="$PSRCDIR/sources_1/imports/src/channel.vhd">
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="mdsynth"/>
@@ -3,14 +3,14 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="impact" timeStamp="Sat Mar 19 16:35:28 2011">
+<application name="impact" timeStamp="Sun May 15 14:56:36 2011">
<section name="Project Information" visible="false">
-<property name="ProjectID" value="c30064f3857d4c1eba90f81ac235f392"/>
+<property name="ProjectID" value="cb7182bb66404587b0e621b2e436b73c"/>
<property name="ProjectIteration" value="1"/>
</section>
<section name="iMPACT Project Info" visible="true">
<property name="Use Project File" value="Yes"/>
-<property name="Project Entry" value="pa"/>
+<property name="Project Entry" value="Stand Alone"/>
<property name="OS Name" value="Microsoft Windows 7"/>
<property name="User Lic. Info" value="204973551_0_0_637"/>
</section>
@@ -29,6 +29,12 @@ This means code written to parse this file will need to be revisited each subseq
<item name="Boundary Scan Operations Statistics">
<property name="BSCAN Operation" value="Program -p 0
"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
</item>
<item name="Cable Summary">
<property name="Cable Type" value="Platform Cable USB"/>
@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Fri Apr 15 20:13:04 2011">
+<application name="pa" timeStamp="Sun May 15 14:55:23 2011">
<section name="Project Information" visible="false">
<property name="ProjectID" value="72bbf75a517545f2adb72ce38855e938" type="ProjectID"/>
-<property name="ProjectIteration" value="4" type="ProjectIteration"/>
+<property name="ProjectIteration" value="10" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
@@ -17,20 +17,27 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
-<property name="ConfigureBitgenRun" value="4" type="JavaHandler"/>
+<property name="AddSrc" value="5" type="JavaHandler"/>
+<property name="ConfigureBitgenRun" value="10" type="JavaHandler"/>
<property name="CreateProject" value="1" type="JavaHandler"/>
-<property name="LaunchImpact" value="8" type="JavaHandler"/>
-<property name="OpenProject" value="4" type="JavaHandler"/>
-<property name="ProjectSettings" value="2" type="JavaHandler"/>
-<property name="RunElaborate" value="6" type="JavaHandler"/>
-<property name="RunImplementation" value="3" type="JavaHandler"/>
-<property name="RunSchematic" value="2" type="JavaHandler"/>
-<property name="RunSynthesis" value="3" type="JavaHandler"/>
-<property name="ToggleViewNavigator" value="5" type="JavaHandler"/>
-<property name="ViewTaskRTLDesign" value="6" type="JavaHandler"/>
+<property name="EditDelete" value="2" type="JavaHandler"/>
+<property name="EditProperties" value="1" type="JavaHandler"/>
+<property name="LaunchImpact" value="9" type="JavaHandler"/>
+<property name="LaunchSimulatorWizard" value="16" type="JavaHandler"/>
+<property name="OpenProject" value="5" type="JavaHandler"/>
+<property name="ProjectSettings" value="3" type="JavaHandler"/>
+<property name="RunElaborate" value="20" type="JavaHandler"/>
+<property name="RunImplementation" value="18" type="JavaHandler"/>
+<property name="RunSchematic" value="4" type="JavaHandler"/>
+<property name="RunSynthesis" value="16" type="JavaHandler"/>
+<property name="SaveFile" value="1" type="JavaHandler"/>
+<property name="ShowView" value="4" type="JavaHandler"/>
+<property name="ToggleViewNavigator" value="9" type="JavaHandler"/>
+<property name="ViewTaskProjectManager" value="8" type="JavaHandler"/>
+<property name="ViewTaskRTLDesign" value="29" type="JavaHandler"/>
</item>
<item name="Other">
-<property name="GuiMode" value="14" type="GuiMode"/>
+<property name="GuiMode" value="18" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="0" type="TclMode"/>
<property name="ISEMode" value="0" type="ISEMode"/>
View
@@ -2,6 +2,7 @@
<Project Version="4" Minor="16">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
+ <FileSet Dir="sim_1" File="fileset.xml"/>
<RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
@@ -0,0 +1,104 @@
+-- MD-Synthesizer
+--
+-- Author: Daniel Cliche (dcliche@meldora.com)
+-- Copyright (c) 2011, Meldora Inc. All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+-- * Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- * Redistributions in binary form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+-- * Neither the name of Meldora Inc. nor the
+-- names of its contributors may be used to endorse or promote products
+-- derived from this software without specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+-- DISCLAIMED. IN NO EVENT SHALL MELDORA INC. BE LIABLE FOR ANY
+-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+--
+-- Based on the Music Box example at www.fpga4fun.com
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+
+entity channel is
+ port ( clk: in std_logic;
+ reset: in std_logic;
+ waveform: in unsigned(1 downto 0); -- 0: None, 1: Square, 2: Sawtooth, 3: Sine
+ pitch: in unsigned(6 downto 0); -- 60 = C4
+ output: out std_logic);
+end channel;
+
+architecture channel_arch of channel is
+
+component dac is
+ port ( clk: in std_logic;
+ dac_in: in std_logic_vector(7 downto 0);
+ reset: in std_logic;
+ dac_out: out std_logic);
+end component;
+
+component sinewave is
+ port ( clk: in std_logic;
+ data_out: out integer range -128 to 127);
+end component;
+
+component pitch_clk_div is
+ port ( clk: std_logic;
+ pitch : in unsigned(6 downto 0); -- 60 = C4
+ output : out std_logic);
+end component;
+
+signal counter : unsigned(15 downto 0) := (others => '0');
+
+signal dac_in : std_logic_vector(7 downto 0);
+signal dac_reset : std_logic;
+signal sine : integer range -128 to 127 := 0;
+signal clk_div_out : std_logic;
+
+
+begin
+
+ pitch_clk_div0 : pitch_clk_div port map (clk => clk, pitch => pitch, output => clk_div_out);
+ sinewave0 : sinewave port map (clk => clk_div_out, data_out => sine);
+ dac0 : dac port map (clk => clk, dac_in => dac_in, reset => reset, dac_out => output);
+
+ process (clk_div_out)
+ begin
+ if (clk_div_out'event and clk_div_out = '1') then
+ counter <= counter + 1;
+ case waveform is
+ when "01" =>
+ -- Square wave
+ if (std_logic(counter(0))= '1') then
+ dac_in(7 downto 0) <= (others => '1');
+ else
+ dac_in(7 downto 0) <= (others => '0');
+ end if;
+ when "10" =>
+ -- Sawtooth wave
+ dac_in <= std_logic_vector(counter(7 downto 0));
+ when "11" =>
+ -- Sine wave
+ dac_in <= conv_std_logic_vector(128 + sine, 8);
+ when others =>
+ dac_in(7 downto 0) <= (others => '0');
+ end case;
+ end if;
+
+ end process;
+
+end channel_arch;
+
@@ -34,39 +34,57 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity div_by_12 is
- Port ( numerator : in unsigned(5 downto 0);
- quotient : out unsigned(2 downto 0);
+ Port ( numerator : in unsigned(6 downto 0);
+ quotient : out unsigned(3 downto 0);
remain : out unsigned(3 downto 0));
end div_by_12;
-architecture Behavioral of div_by_12 is
-signal r: unsigned(3 downto 0);
+architecture div_by_12_arch of div_by_12 is
+signal r: unsigned(1 downto 0);
begin
- process (numerator(5 downto 2))
+ -- We divide by 3 on the remaining bits
+ process (numerator(6 downto 2))
begin
- case numerator(5 downto 2) is
- when "0000" => r <= "0000";
- when "0001" => r <= "0001";
- when "0010" => r <= "0010";
- when "0011" => r <= "0000";
- when "0100" => r <= "0001";
- when "0101" => r <= "0010";
- when "0110" => r <= "0000";
- when "0111" => r <= "0001";
- when "1000" => r <= "0010";
- when "1001" => r <= "0000";
- when "1010" => r <= "0001";
- when "1011" => r <= "0010";
- when "1100" => r <= "0000";
- when "1101" => r <= "0001";
- when "1110" => r <= "0010";
- when "1111" => r <= "0000";
- when others => r <= "0000"; -- Should not happen
+ case numerator(6 downto 2) is
+ when "00000" => quotient <= "0000"; r <= "00";
+ when "00001" => quotient <= "0000"; r <= "01";
+ when "00010" => quotient <= "0000"; r <= "10";
+ when "00011" => quotient <= "0001"; r <= "00";
+ when "00100" => quotient <= "0001"; r <= "01";
+ when "00101" => quotient <= "0001"; r <= "10";
+ when "00110" => quotient <= "0010"; r <= "00";
+ when "00111" => quotient <= "0010"; r <= "01";
+ when "01000" => quotient <= "0010"; r <= "10";
+ when "01001" => quotient <= "0011"; r <= "00";
+ when "01010" => quotient <= "0011"; r <= "01";
+ when "01011" => quotient <= "0011"; r <= "10";
+ when "01100" => quotient <= "0100"; r <= "00";
+ when "01101" => quotient <= "0100"; r <= "01";
+ when "01110" => quotient <= "0100"; r <= "10";
+ when "01111" => quotient <= "0101"; r <= "00";
+ when "10000" => quotient <= "0101"; r <= "01";
+ when "10001" => quotient <= "0101"; r <= "10";
+ when "10010" => quotient <= "0110"; r <= "00";
+ when "10011" => quotient <= "0110"; r <= "01";
+ when "10100" => quotient <= "0110"; r <= "10";
+ when "10101" => quotient <= "0111"; r <= "00";
+ when "10110" => quotient <= "0111"; r <= "01";
+ when "10111" => quotient <= "0111"; r <= "10";
+ when "11000" => quotient <= "1000"; r <= "00";
+ when "11001" => quotient <= "1000"; r <= "01";
+ when "11010" => quotient <= "1000"; r <= "10";
+ when "11011" => quotient <= "1001"; r <= "00";
+ when "11100" => quotient <= "1001"; r <= "01";
+ when "11101" => quotient <= "1001"; r <= "10";
+ when "11110" => quotient <= "1010"; r <= "00";
+ when "11111" => quotient <= "1010"; r <= "01";
+
+ when others => quotient <= "0000"; r <= "00"; -- Should not happen
end case;
end process;
- remain <= r(3) & r(2) & numerator(1 downto 0);
+ remain <= r(1) & r(0) & numerator(1 downto 0);
-end Behavioral;
+end div_by_12_arch;
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