Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with
or
.
Download ZIP

Comparing changes

Choose two branches to see what's changed or to start a new pull request. If you need to, you can also compare across forks.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also compare across forks.
base fork: dcliche/mdsynth
base: a4a522ff4f
...
head fork: dcliche/mdsynth
compare: f7ea415693
  • 2 commits
  • 29 files changed
  • 0 commit comments
  • 1 contributor
Commits on Jun 23, 2011
unknown - The MIDI pitch conversion is now done in a separate component. df0043d
Commits on Jun 24, 2011
unknown - Phase modulation added;
- We now have only the quarter of of sine.
f7ea415
Showing with 669 additions and 117 deletions.
  1. +1 −0  .gitignore
  2. +14 −11 README.txt
  3. BIN  mdsynth.data/auto_project.ipf
  4. BIN  mdsynth.data/impact/impactdefaultproj.ipf
  5. +3 −3 mdsynth.data/impact_impact.xwbt
  6. +20 −0 mdsynth.data/runs.new/impl_1.psg
  7. +17 −0 mdsynth.data/runs.new/impl_1/constrs_in.xml
  8. +37 −0 mdsynth.data/runs.new/runs.xml
  9. +9 −0 mdsynth.data/runs.new/synth_1.psg
  10. +17 −0 mdsynth.data/runs.new/synth_1/constrs_in.xml
  11. +41 −0 mdsynth.data/runs.new/synth_1/sources.xml
  12. +12 −0 mdsynth.data/runs/impl_1/constrs_out.xml
  13. +2 −2 mdsynth.data/runs/runs.xml
  14. +2 −0  mdsynth.data/runs/synth_1/sources.xml
  15. +18 −0 mdsynth.data/runs_2.new/impl_1.psg
  16. +17 −0 mdsynth.data/runs_2.new/impl_1/constrs_in.xml
  17. +37 −0 mdsynth.data/runs_2.new/runs.xml
  18. +9 −0 mdsynth.data/runs_2.new/synth_1.psg
  19. +17 −0 mdsynth.data/runs_2.new/synth_1/constrs_in.xml
  20. +41 −0 mdsynth.data/runs_2.new/synth_1/sources.xml
  21. +2 −0  mdsynth.data/sources_1/fileset.xml
  22. +22 −8 mdsynth.data/webtalk_impact.xml
  23. +21 −14 mdsynth.data/wt/webtalk_pa.xml
  24. +47 −16 mdsynth.srcs/sources_1/imports/src/channel.vhd
  25. +9 −7 mdsynth.srcs/sources_1/imports/src/mdsynth.vhd
  26. +14 −4 mdsynth.srcs/sources_1/imports/src/sinewave.vhd
  27. +8 −52 mdsynth.srcs/sources_1/new/nco.vhd
  28. +95 −0 mdsynth.srcs/sources_1/new/pitch_to_freq.vhd
  29. +137 −0 planAhead.jou
View
1  .gitignore
@@ -1,2 +1,3 @@
mdsynth.runs
mdsynth.sim
+*.log
View
25 README.txt
@@ -25,23 +25,26 @@ The projet has been converted to Xilinx PlanAhead 13.1.
Waveform selection
------------------
-SW0 SW1 Waveform
--- -- --------
-0 0 None
-0 1 Square
-1 0 Sawtooth
-1 1 Sine
+SW0 SW1 SW2 Waveform
+--- --- --- --------
+0 0 0 None
+0 1 0 Square (message only)
+1 0 0 Sawtooth (message only)
+1 1 0 Sine (message only)
+0 0 1 Frequency Modulation (implemented as phase modulation for simplicity)
Pitch
-----
The pitch is MIDI compatible. The value is between 0 and 127, 69 being A4 at 440Hz.
-Implementation Notes
---------------------
+Phase Modulation
+----------------
-I am now using an numerically-controlled oscillator (NCO) in order to produce a phase value used as an index of the sine table. This is much simpler, less restrictive and is a better design because we keep the clock intact.
+The formula is the following: y(t) = sin(m(t) + 2*pi*freq_carrier*t)
+where m(t) = sin(2*pi*freq_message*t)
-Right now, the sine table is a complete 2*PI cycle. I will eventually use only a quarter of it in order to reduce the footprint.
+Implementation Notes
+--------------------
-The NCO decode the MIDI pitch value, but we may want to split this and provide to the NCO a frequency value instead for more flexibility.
+I am using an numerically-controlled oscillator (NCO) in order to produce a phase value used as an index of the sine table.
View
BIN  mdsynth.data/auto_project.ipf
Binary file not shown
View
BIN  mdsynth.data/impact/impactdefaultproj.ipf
Binary file not shown
View
6 mdsynth.data/impact_impact.xwbt
@@ -1,8 +1,8 @@
INTSTYLE=impact
-INFILE=C:\Users\Public\Documents\Xilinx\mdsynth\mdsynth.data\impact.xsl
-OUTFILE=C:\Users\Public\Documents\Xilinx\mdsynth\mdsynth.data\impact.xsl
+INFILE=C:\Users\dev\Xilinx\mdsynth\mdsynth.data\impact.xsl
+OUTFILE=C:\Users\dev\Xilinx\mdsynth\mdsynth.data\impact.xsl
FAMILY=Multiple
PART=Multiple
-WORKINGDIR=C:\Users\Public\Documents\Xilinx\mdsynth\mdsynth.data
+WORKINGDIR=C:\Users\dev\Xilinx\mdsynth\mdsynth.data
LICENSE=iMPACT
USER_INFO=iMPACT
View
20 mdsynth.data/runs.new/impl_1.psg
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+ <StratHandle Name="ISE Defaults" Flow="ISE13">
+ <Desc>ISE Defaults, including packing registers in IOs off</Desc>
+ </StratHandle>
+ <Step Id="ngdbuild">
+ </Step>
+ <Step Id="map">
+ <Option Id="FFPackEnum">3</Option>
+ </Step>
+ <Step Id="par">
+ </Step>
+ <Step Id="trce">
+ </Step>
+ <Step Id="xdl">
+ </Step>
+ <Step Id="bitgen">
+ </Step>
+</Strategy>
+
View
17 mdsynth.data/runs.new/impl_1/constrs_in.xml
@@ -0,0 +1,17 @@
+<?xml version="1.0"?>
+<DARoots Version="1" Minor="12">
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PSRCDIR/constrs_1/imports/src/s3astarter.ucf">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/s3astarter.ucf"/>
+ <Attr Name="ImportTime" Val="1300047501"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/imports/src/s3astarter.ucf"/>
+ <Option Name="TargetPart" Val="xc3s700afg484-4"/>
+ </Config>
+ </FileSet>
+</DARoots>
+
View
37 mdsynth.data/runs.new/runs.xml
@@ -0,0 +1,37 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="6">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc3s700afg484-4" ConstrsSet="constrs_1" State="current" Dir="$PRUNDIR/synth_1" LaunchTime="1308945476">
+ <File Type="PA-XST" Name="mdsynth.xst"/>
+ <File Type="RUN-SRCS" Name="$PDATADIR/runs/synth_1/sources.xml"/>
+ <File Type="XST-NGC" Name="mdsynth.ngc"/>
+ <File Type="PA-XSTPRJ" Name="mdsynth.prj"/>
+ <File Type="RUN-CONSTRS" Name="$PDATADIR/runs/synth_1/constrs_in.xml"/>
+ <File Type="XST-SRP" Name="mdsynth.srp"/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" SynthRun="synth_1" Part="xc3s700afg484-4" ConstrsSet="constrs_1" State="current" Dir="$PRUNDIR/impl_1" LaunchTime="1308945495">
+ <File Type="PA-EDIF" Name="mdsynth.edf"/>
+ <File Type="PAR-PAD" Name="mdsynth_routed_pad.txt"/>
+ <File Type="PA-UCF" Name="mdsynth.ucf"/>
+ <File Type="PAR-PAR" Name="mdsynth_routed.par"/>
+ <File Type="PAR-UNR" Name="mdsynth_routed.unroutes"/>
+ <File Type="BG-BIT" Name="mdsynth.bit"/>
+ <File Type="BG-DRC" Name="mdsynth.drc"/>
+ <File Type="BG-BGN" Name="mdsynth.bgn"/>
+ <File Type="TRCE-TWR" Name="mdsynth.twr"/>
+ <File Type="PA-CONSTRSDIR" Name=".constrs"/>
+ <File Type="TRCE-TWX" Name="mdsynth.twx"/>
+ <File Type="XDL-XDL" Name="mdsynth_routed.xdl"/>
+ <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+ <File Type="WBT-LOG" Name="webtalk.log"/>
+ <File Type="RUN-CONSTRS" Name="$PDATADIR/runs/impl_1/constrs_in.xml"/>
+ <File Type="NGDB-NGD" Name="mdsynth.ngd"/>
+ <File Type="NGDB-BLD" Name="mdsynth.bld"/>
+ <File Type="MAP-NCD" Name="mdsynth.ncd"/>
+ <File Type="MAP-PCF" Name="mdsynth.pcf"/>
+ <File Type="MAP-MRP" Name="mdsynth.mrp"/>
+ <File Type="MAP-MAP" Name="mdsynth.map"/>
+ <File Type="MAP-PSR" Name="mdsynth.psr"/>
+ <File Type="PAR-NCD" Name="mdsynth_routed.ncd"/>
+ </Run>
+</Runs>
+
View
9 mdsynth.data/runs.new/synth_1.psg
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+ <StratHandle Name="PlanAhead Defaults" Flow="XST13">
+ <Desc>PlanAhead Defaults (XST defaults with hierarchy)</Desc>
+ </StratHandle>
+ <Step Id="xst">
+ </Step>
+</Strategy>
+
View
17 mdsynth.data/runs.new/synth_1/constrs_in.xml
@@ -0,0 +1,17 @@
+<?xml version="1.0"?>
+<DARoots Version="1" Minor="12">
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PSRCDIR/constrs_1/imports/src/s3astarter.ucf">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/s3astarter.ucf"/>
+ <Attr Name="ImportTime" Val="1300047501"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/imports/src/s3astarter.ucf"/>
+ <Option Name="TargetPart" Val="xc3s700afg484-4"/>
+ </Config>
+ </FileSet>
+</DARoots>
+
View
41 mdsynth.data/runs.new/synth_1/sources.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0"?>
+<DARoots Version="1" Minor="12">
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/sources_1/imports/src/dac.vhd">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/dac.vhd"/>
+ <Attr Name="ImportTime" Val="1297455010"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/imports/src/div_by_12.vhd">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/div_by_12.vhd"/>
+ <Attr Name="ImportTime" Val="1299777942"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/imports/src/mdsynth.vhd">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/mdsynth.vhd"/>
+ <Attr Name="ImportTime" Val="1299885873"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/imports/src/sinewave.vhd">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/sinewave.vhd"/>
+ <Attr Name="ImportTime" Val="1299797437"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/imports/src/channel.vhd">
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/nco.vhd">
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/pitch_to_freq.vhd">
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="mdsynth"/>
+ </Config>
+ </FileSet>
+</DARoots>
+
View
12 mdsynth.data/runs/impl_1/constrs_out.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<DARoots Version="1" Minor="12">
+ <FileSet Name="constrs_out" Type="Constrs" RelSrcDir="$PRUNDIR/impl_1/.constrs">
+ <File Path="$PRUNDIR/impl_1/.constrs/s3astarter.ucf">
+ </File>
+ <Config>
+ <Option Name="TargetConstrsFile" Val="$PRUNDIR/impl_1/.constrs/s3astarter.ucf"/>
+ <Option Name="TargetPart" Val="xc3s700afg484-4"/>
+ </Config>
+ </FileSet>
+</DARoots>
+
View
4 mdsynth.data/runs/runs.xml
@@ -1,6 +1,6 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="6">
- <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc3s700afg484-4" ConstrsSet="constrs_1" State="current" Dir="$PRUNDIR/synth_1" LaunchTime="1306704110">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc3s700afg484-4" ConstrsSet="constrs_1" State="current" Dir="$PRUNDIR/synth_1" LaunchTime="1308954092">
<File Type="PA-XST" Name="mdsynth.xst"/>
<File Type="RUN-SRCS" Name="$PDATADIR/runs/synth_1/sources.xml"/>
<File Type="XST-NGC" Name="mdsynth.ngc"/>
@@ -8,7 +8,7 @@
<File Type="RUN-CONSTRS" Name="$PDATADIR/runs/synth_1/constrs_in.xml"/>
<File Type="XST-SRP" Name="mdsynth.srp"/>
</Run>
- <Run Id="impl_1" Type="Ft2:EntireDesign" SynthRun="synth_1" Part="xc3s700afg484-4" ConstrsSet="constrs_1" State="current" Dir="$PRUNDIR/impl_1" LaunchTime="1306704140">
+ <Run Id="impl_1" Type="Ft2:EntireDesign" SynthRun="synth_1" Part="xc3s700afg484-4" ConstrsSet="constrs_1" State="current" Dir="$PRUNDIR/impl_1" LaunchTime="1308954117">
<File Type="PA-EDIF" Name="mdsynth.edf"/>
<File Type="PAR-PAD" Name="mdsynth_routed_pad.txt"/>
<File Type="PA-UCF" Name="mdsynth.ucf"/>
View
2  mdsynth.data/runs/synth_1/sources.xml
@@ -30,6 +30,8 @@
</File>
<File Path="$PSRCDIR/sources_1/new/nco.vhd">
</File>
+ <File Path="$PSRCDIR/sources_1/new/pitch_to_freq.vhd">
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="mdsynth"/>
View
18 mdsynth.data/runs_2.new/impl_1.psg
@@ -0,0 +1,18 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+ <StratHandle Name="ISE Defaults" Flow="ISE13">
+ <Desc>ISE Defaults, including packing registers in IOs off</Desc>
+ </StratHandle>
+ <Step Id="ngdbuild">
+ </Step>
+ <Step Id="map">
+ <Option Id="FFPackEnum">3</Option>
+ </Step>
+ <Step Id="par">
+ </Step>
+ <Step Id="trce">
+ </Step>
+ <Step Id="xdl">
+ </Step>
+</Strategy>
+
View
17 mdsynth.data/runs_2.new/impl_1/constrs_in.xml
@@ -0,0 +1,17 @@
+<?xml version="1.0"?>
+<DARoots Version="1" Minor="12">
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PSRCDIR/constrs_1/imports/src/s3astarter.ucf">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/s3astarter.ucf"/>
+ <Attr Name="ImportTime" Val="1300047501"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/imports/src/s3astarter.ucf"/>
+ <Option Name="TargetPart" Val="xc3s700afg484-4"/>
+ </Config>
+ </FileSet>
+</DARoots>
+
View
37 mdsynth.data/runs_2.new/runs.xml
@@ -0,0 +1,37 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="6">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc3s700afg484-4" ConstrsSet="constrs_1" State="current" Dir="$PRUNDIR/synth_1" LaunchTime="1308946325">
+ <File Type="PA-XST" Name="mdsynth.xst"/>
+ <File Type="RUN-SRCS" Name="$PDATADIR/runs/synth_1/sources.xml"/>
+ <File Type="XST-NGC" Name="mdsynth.ngc"/>
+ <File Type="PA-XSTPRJ" Name="mdsynth.prj"/>
+ <File Type="RUN-CONSTRS" Name="$PDATADIR/runs/synth_1/constrs_in.xml"/>
+ <File Type="XST-SRP" Name="mdsynth.srp"/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" SynthRun="synth_1" Part="xc3s700afg484-4" ConstrsSet="constrs_1" State="current" Dir="$PRUNDIR/impl_1" LaunchTime="1308946344">
+ <File Type="PA-EDIF" Name="mdsynth.edf"/>
+ <File Type="PAR-PAD" Name="mdsynth_routed_pad.txt"/>
+ <File Type="PA-UCF" Name="mdsynth.ucf"/>
+ <File Type="PAR-PAR" Name="mdsynth_routed.par"/>
+ <File Type="PAR-UNR" Name="mdsynth_routed.unroutes"/>
+ <File Type="BG-BIT" Name="mdsynth.bit"/>
+ <File Type="BG-DRC" Name="mdsynth.drc"/>
+ <File Type="BG-BGN" Name="mdsynth.bgn"/>
+ <File Type="TRCE-TWR" Name="mdsynth.twr"/>
+ <File Type="PA-CONSTRSDIR" Name=".constrs"/>
+ <File Type="TRCE-TWX" Name="mdsynth.twx"/>
+ <File Type="XDL-XDL" Name="mdsynth_routed.xdl"/>
+ <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+ <File Type="WBT-LOG" Name="webtalk.log"/>
+ <File Type="RUN-CONSTRS" Name="$PDATADIR/runs/impl_1/constrs_in.xml"/>
+ <File Type="NGDB-NGD" Name="mdsynth.ngd"/>
+ <File Type="NGDB-BLD" Name="mdsynth.bld"/>
+ <File Type="MAP-NCD" Name="mdsynth.ncd"/>
+ <File Type="MAP-PCF" Name="mdsynth.pcf"/>
+ <File Type="MAP-MRP" Name="mdsynth.mrp"/>
+ <File Type="MAP-MAP" Name="mdsynth.map"/>
+ <File Type="MAP-PSR" Name="mdsynth.psr"/>
+ <File Type="PAR-NCD" Name="mdsynth_routed.ncd"/>
+ </Run>
+</Runs>
+
View
9 mdsynth.data/runs_2.new/synth_1.psg
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+ <StratHandle Name="PlanAhead Defaults" Flow="XST13">
+ <Desc>PlanAhead Defaults (XST defaults with hierarchy)</Desc>
+ </StratHandle>
+ <Step Id="xst">
+ </Step>
+</Strategy>
+
View
17 mdsynth.data/runs_2.new/synth_1/constrs_in.xml
@@ -0,0 +1,17 @@
+<?xml version="1.0"?>
+<DARoots Version="1" Minor="12">
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PSRCDIR/constrs_1/imports/src/s3astarter.ucf">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/s3astarter.ucf"/>
+ <Attr Name="ImportTime" Val="1300047501"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/imports/src/s3astarter.ucf"/>
+ <Option Name="TargetPart" Val="xc3s700afg484-4"/>
+ </Config>
+ </FileSet>
+</DARoots>
+
View
41 mdsynth.data/runs_2.new/synth_1/sources.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0"?>
+<DARoots Version="1" Minor="12">
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/sources_1/imports/src/dac.vhd">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/dac.vhd"/>
+ <Attr Name="ImportTime" Val="1297455010"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/imports/src/div_by_12.vhd">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/div_by_12.vhd"/>
+ <Attr Name="ImportTime" Val="1299777942"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/imports/src/mdsynth.vhd">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/mdsynth.vhd"/>
+ <Attr Name="ImportTime" Val="1299885873"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/imports/src/sinewave.vhd">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Xilinx/mdsynth/src/sinewave.vhd"/>
+ <Attr Name="ImportTime" Val="1299797437"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/imports/src/channel.vhd">
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/nco.vhd">
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/pitch_to_freq.vhd">
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="mdsynth"/>
+ </Config>
+ </FileSet>
+</DARoots>
+
View
2  mdsynth.data/sources_1/fileset.xml
@@ -30,6 +30,8 @@
</File>
<File Path="$PSRCDIR/sources_1/new/nco.vhd">
</File>
+ <File Path="$PSRCDIR/sources_1/new/pitch_to_freq.vhd">
+ </File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="mdsynth"/>
View
30 mdsynth.data/webtalk_impact.xml
@@ -3,16 +3,16 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="impact" timeStamp="Sun May 29 17:40:30 2011">
+<application name="impact" timeStamp="Fri Jun 24 18:29:46 2011">
<section name="Project Information" visible="false">
-<property name="ProjectID" value="3e64042f9be743a0a598d738897e4b12"/>
+<property name="ProjectID" value="cd2b1fb042a74368b77a0d047e04d091"/>
<property name="ProjectIteration" value="1"/>
</section>
<section name="iMPACT Project Info" visible="true">
<property name="Use Project File" value="Yes"/>
-<property name="Project Entry" value="Stand Alone"/>
-<property name="OS Name" value="Microsoft Windows 7"/>
-<property name="User Lic. Info" value="204973551_0_0_637"/>
+<property name="Project Entry" value="pa"/>
+<property name="OS Name" value="Microsoft Windows 7 (64 Bit)"/>
+<property name="User Lic. Info" value="204973551_0_0_873"/>
</section>
<section name="iMPACT One Step SVF File Mode" visible="true">
<item name="Chain Summary">
@@ -35,11 +35,25 @@ This means code written to parse this file will need to be revisited each subseq
"/>
<property name="BSCAN Operation" value="Program -p 0
"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
</item>
<item name="Cable Summary">
-<property name="Cable Type" value=""/>
-<property name="Cable Speed" value="0"/>
-<property name="Port" value="NULL"/>
+<property name="Cable Type" value="Platform Cable USB"/>
+<property name="Cable Speed" value="6 MHz"/>
+<property name="Port" value="usb-hs"/>
<property name="Local_Server_Mode" value="Local"/>
</item>
</section>
View
35 mdsynth.data/wt/webtalk_pa.xml
@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Sun May 29 17:37:38 2011">
+<application name="pa" timeStamp="Fri Jun 24 18:29:37 2011">
<section name="Project Information" visible="false">
<property name="ProjectID" value="72bbf75a517545f2adb72ce38855e938" type="ProjectID"/>
-<property name="ProjectIteration" value="13" type="ProjectIteration"/>
+<property name="ProjectIteration" value="24" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
@@ -17,29 +17,36 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
-<property name="AddSrc" value="6" type="JavaHandler"/>
-<property name="ConfigureBitgenRun" value="13" type="JavaHandler"/>
+<property name="AddSrc" value="8" type="JavaHandler"/>
+<property name="ConfigureBitgenRun" value="24" type="JavaHandler"/>
<property name="CreateProject" value="1" type="JavaHandler"/>
+<property name="CreateSrc" value="8" type="JavaHandler"/>
<property name="EditDelete" value="3" type="JavaHandler"/>
<property name="EditProperties" value="2" type="JavaHandler"/>
<property name="FileExit" value="2" type="JavaHandler"/>
-<property name="LaunchImpact" value="9" type="JavaHandler"/>
-<property name="LaunchSimulatorWizard" value="18" type="JavaHandler"/>
+<property name="LaunchImpact" value="13" type="JavaHandler"/>
+<property name="LaunchSimulatorWizard" value="21" type="JavaHandler"/>
+<property name="OpenDesign" value="1" type="JavaHandler"/>
<property name="OpenProject" value="5" type="JavaHandler"/>
<property name="ProjectSettings" value="3" type="JavaHandler"/>
-<property name="RunElaborate" value="45" type="JavaHandler"/>
-<property name="RunImplementation" value="22" type="JavaHandler"/>
-<property name="RunSchematic" value="4" type="JavaHandler"/>
-<property name="RunSynthesis" value="33" type="JavaHandler"/>
+<property name="ResourceEstimation" value="1" type="JavaHandler"/>
+<property name="RunElaborate" value="50" type="JavaHandler"/>
+<property name="RunImplementation" value="41" type="JavaHandler"/>
+<property name="RunSchematic" value="6" type="JavaHandler"/>
+<property name="RunSynthesis" value="64" type="JavaHandler"/>
<property name="SaveFile" value="1" type="JavaHandler"/>
-<property name="ShowView" value="13" type="JavaHandler"/>
+<property name="ShowView" value="28" type="JavaHandler"/>
+<property name="ToggleCreateBELConstrainMode" value="2" type="JavaHandler"/>
+<property name="ToggleCreatePblockMode" value="7" type="JavaHandler"/>
<property name="ToggleViewNavigator" value="9" type="JavaHandler"/>
<property name="ToolsOptions" value="1" type="JavaHandler"/>
-<property name="ViewTaskProjectManager" value="13" type="JavaHandler"/>
-<property name="ViewTaskRTLDesign" value="59" type="JavaHandler"/>
+<property name="UnhighlightSelection" value="2" type="JavaHandler"/>
+<property name="ViewTaskImplementedDesign" value="2" type="JavaHandler"/>
+<property name="ViewTaskProjectManager" value="18" type="JavaHandler"/>
+<property name="ViewTaskRTLDesign" value="67" type="JavaHandler"/>
</item>
<item name="Other">
-<property name="GuiMode" value="21" type="GuiMode"/>
+<property name="GuiMode" value="24" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="0" type="TclMode"/>
<property name="ISEMode" value="0" type="ISEMode"/>
View
63 mdsynth.srcs/sources_1/imports/src/channel.vhd
@@ -32,8 +32,9 @@ use IEEE.NUMERIC_STD.ALL;
entity channel is
port ( clk: in std_logic;
reset: in std_logic;
- waveform: in std_logic_vector(1 downto 0); -- 0: None, 1: Square, 2: Sawtooth, 3: Sine
- pitch: in unsigned(6 downto 0); -- 60 = C4
+ waveform: in std_logic_vector(2 downto 0); -- 0: None, 1: Square (message only), 2: Sawtooth (message only), 3: Sine (message only), 4: FM (implemented as phase modulation)
+ pitch_message: in unsigned(6 downto 0); -- 60 = C4
+ pitch_carrier: in unsigned(6 downto 0); -- 60 = C4
output: out std_logic);
end channel;
@@ -51,42 +52,72 @@ component sinewave is
data_out: out integer range -128 to 127);
end component;
+component pitch_to_freq is
+ port ( pitch: in unsigned(6 downto 0); -- 60 = C4
+ phase_delta: out unsigned(11 downto 0);
+ octave: out unsigned(3 downto 0));
+end component;
+
component nco is
- port ( clk: in std_logic;
- pitch: in unsigned(6 downto 0); -- 60 = C4
- phase: out unsigned(7 downto 0));
+ port ( clk: in std_logic;
+ phase_delta: in unsigned(11 downto 0);
+ octave: in unsigned(3 downto 0);
+ phase: out unsigned(7 downto 0));
end component;
signal counter : unsigned(15 downto 0) := (others => '0');
signal dac_in : std_logic_vector(7 downto 0);
-signal phase : unsigned(7 downto 0);
-signal sine : integer range -128 to 127 := 0;
+
+signal phase_delta_carrier : unsigned(11 downto 0);
+signal phase_delta_message : unsigned(11 downto 0);
+
+signal octave_carrier : unsigned(3 downto 0);
+signal octave_message : unsigned(3 downto 0);
+
+signal phase_carrier : unsigned(7 downto 0);
+signal phase_message : unsigned(7 downto 0);
+signal phase_modulated : unsigned(7 downto 0);
+
+signal sine_message : integer range -128 to 127 := 0;
+signal sine_modulated : integer range -128 to 127 := 0;
begin
- nco0 : nco port map (clk => clk, pitch => pitch, phase => phase);
- sinewave0 : sinewave port map (phase => phase, data_out => sine);
- dac0 : dac port map (clk => clk, dac_in => dac_in, reset => reset, dac_out => output);
+ pitch_to_freq_message0 : pitch_to_freq port map (pitch => pitch_message, phase_delta => phase_delta_message, octave => octave_message);
+ pitch_to_freq_carrier0 : pitch_to_freq port map (pitch => pitch_carrier, phase_delta => phase_delta_carrier, octave => octave_carrier);
+
+ nco_carrier0 : nco port map (clk => clk, phase_delta => phase_delta_carrier, octave => octave_carrier, phase => phase_carrier);
+ nco_message0 : nco port map (clk => clk, phase_delta => phase_delta_message, octave => octave_message, phase => phase_message);
+
+ sinewave_message0 : sinewave port map (phase => phase_message, data_out => sine_message);
+ sinewave_modulated0 : sinewave port map (phase => phase_modulated, data_out => sine_modulated);
+ dac0 : dac port map (clk => clk, dac_in => dac_in, reset => reset, dac_out => output);
+
+ phase_modulated <= phase_carrier + sine_message;
+
process (clk)
begin
if (rising_edge(clk)) then
counter <= counter + 1;
case waveform is
- when "01" =>
+ when "001" =>
-- Square wave
- if (phase(7) = '1') then
+ if (phase_message(7) = '1') then
dac_in(7 downto 0) <= (others => '1');
else
dac_in(7 downto 0) <= (others => '0');
end if;
- when "10" =>
+ when "010" =>
-- Sawtooth wave
- dac_in <= std_logic_vector(phase);
- when "11" =>
+ dac_in <= std_logic_vector(phase_message);
+ when "011" =>
-- Sine wave
- dac_in <= std_logic_vector(to_unsigned(128 + sine, 8));
+ dac_in <= std_logic_vector(to_unsigned(128 + sine_message, 8));
+ when "100" =>
+ -- FM (implemented as phase modulation)
+ dac_in <= std_logic_vector(to_unsigned(128 + sine_modulated, 8));
when others =>
dac_in(7 downto 0) <= (others => '0');
end case;
View
16 mdsynth.srcs/sources_1/imports/src/mdsynth.vhd
@@ -46,21 +46,23 @@ architecture mdsynth_arch of mdsynth is
component channel is
port ( clk: in std_logic;
reset: in std_logic;
- waveform: in std_logic_vector(1 downto 0); -- 0: None, 1: Square, 2: Sawtooth, 3: Sine
- pitch: in unsigned(6 downto 0); -- 60 = C4
+ waveform: in std_logic_vector(2 downto 0); -- 0: None, 1: Square, 2: Sawtooth, 3: Sine, 4: FM
+ pitch_message: in unsigned(6 downto 0); -- 60 = C4
+ pitch_carrier: in unsigned(6 downto 0); -- 60 = C4
output: out std_logic);
end component;
signal channel_out: std_logic;
-signal pitch: unsigned (6 downto 0) := to_unsigned(69, 7);
+signal pitch_message: unsigned (6 downto 0) := to_unsigned(69, 7);
+signal pitch_carrier: unsigned (6 downto 0) := to_unsigned(10, 7);
signal counter: unsigned (31 downto 0) := to_unsigned(0, 32);
-signal waveform: std_logic_vector(1 downto 0) := "11";
+signal waveform: std_logic_vector(2 downto 0) := "100";
begin
- channel0: channel port map (clk => clk, reset => btn_south, waveform => waveform, pitch => pitch, output => channel_out);
+ channel0: channel port map (clk => clk, reset => btn_south, waveform => waveform, pitch_message => pitch_message, pitch_carrier => pitch_carrier, output => channel_out);
- waveform <= switch(1 downto 0);
+ waveform <= switch(2 downto 0);
aud_l <= channel_out;
aud_r <= channel_out;
@@ -72,7 +74,7 @@ begin
if (rising_edge(clk)) then
if (counter = 0) then
counter <= to_unsigned(5000000, 32);
- pitch <= pitch + 1;
+ pitch_message <= pitch_message + 1;
else
counter <= counter - 1;
end if;
View
18 mdsynth.srcs/sources_1/imports/src/sinewave.vhd
@@ -35,10 +35,20 @@ entity sinewave is
end sinewave;
architecture Behavioral of sinewave is
-signal i : integer range 0 to 30:=0;
-type memory_type is array (0 to 255) of integer range -128 to 127;
-signal sine : memory_type :=(0,3,6,9,12,15,18,21,24,28,31,34,37,40,43,46,48,51,54,57,60,63,65,68,71,73,76,78,81,83,85,88,90,92,94,96,98,100,102,104,106,108,109,111,112,114,115,117,118,119,120,121,122,123,124,124,125,126,126,127,127,127,127,127,127,127,127,127,127,127,126,126,125,124,124,123,122,121,120,119,118,117,115,114,112,111,109,108,106,104,102,100,98,96,94,92,90,88,85,83,81,78,76,73,71,68,65,63,60,57,54,51,48,46,43,40,37,34,31,28,24,21,18,15,12,9,6,3,0,-4,-7,-10,-13,-16,-19,-22,-25,-29,-32,-35,-38,-41,-44,-47,-49,-52,-55,-58,-61,-64,-66,-69,-72,-74,-77,-79,-82,-84,-86,-89,-91,-93,-95,-97,-99,-101,-103,-105,-107,-109,-110,-112,-113,-115,-116,-118,-119,-120,-121,-122,-123,-124,-125,-125,-126,-127,-127,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-128,-127,-127,-126,-125,-125,-124,-123,-122,-121,-120,-119,-118,-116,-115,-113,-112,-110,-109,-107,-105,-103,-101,-99,-97,-95,-93,-91,-89,-86,-84,-82,-79,-77,-74,-72,-69,-66,-64,-61,-58,-55,-52,-49,-47,-44,-41,-38,-35,-32,-29,-25,-22,-19,-16,-13,-10,-7,-4);
+type memory_type is array (0 to 63) of integer range -128 to 127;
+signal sine : memory_type :=(0,3,6,9,12,15,18,21,24,28,31,34,37,40,43,46,48,51,54,57,60,63,65,68,71,73,76,78,81,83,85,88,90,92,94,96,98,100,102,104,106,108,109,111,112,114,115,117,118,119,120,121,122,123,124,124,125,126,126,127,127,127,127,127);
begin
- data_out <= sine(to_integer(phase));
+ process(phase)
+ begin
+ if (phase < 64) then
+ data_out <= sine(to_integer(phase));
+ elsif (phase >= 64 and phase < 128) then
+ data_out <= sine(63 - (to_integer(phase) - 64));
+ elsif (phase >= 128 and phase < 192) then
+ data_out <= -sine(to_integer(phase) - 128);
+ else -- phase >= 192 and phase < 255
+ data_out <= -sine(63 - (to_integer(phase) - 192));
+ end if;
+ end process;
end Behavioral;
View
60 mdsynth.srcs/sources_1/new/nco.vhd
@@ -26,79 +26,35 @@
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--- Numerically-controlled oscillator with MIDI-compatible pitch input
+-- Numerically-controlled oscillator
--
-
-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
+-- freq = (50E6 * (phase_delta * 2^octave)) / 2^32
entity nco is
port ( clk: in std_logic;
- pitch: in unsigned(6 downto 0); -- 60 = C4
+ phase_delta: in unsigned(11 downto 0);
+ octave: in unsigned(3 downto 0);
phase: out unsigned(7 downto 0));
end nco;
architecture nco_arch of nco is
-component div_by_12 is
- port ( numerator : in unsigned(6 downto 0);
- quotient : out unsigned(3 downto 0);
- remain : out unsigned(3 downto 0));
-end component;
-
-signal octave: unsigned(3 downto 0);
-signal note: unsigned(3 downto 0);
-
signal phase_accumulator: unsigned(31 downto 0) := to_unsigned(0, 32);
-signal phase_delta: unsigned(31 downto 0) := to_unsigned(0, 32);
-
-signal toggle: std_logic := '0';
+signal toggle: std_logic := '0' ;
+signal phase_delta_32: unsigned(31 downto 0) := to_unsigned(0, 32);
begin
- div0: div_by_12 port map (numerator => pitch, quotient => octave, remain => note);
-
- -- pitch 69 (A4) will give the following: octave=5, note=9
- -- The desired frequencies for octave 5 are the following:
- -- note freq (Hz)
- -- 0 261.63 (C4)
- -- 1 277.18
- -- 2 293.66
- -- 3 311.13
- -- 4 329.63
- -- 5 349.23
- -- 6 369.99
- -- 7 392.00
- -- 8 415.30
- -- 9 440.00 (A4)
- -- 10 466.16
- -- 11 493.88
- process (note)
- begin
- case note is
- when "0000" => phase_delta <= to_unsigned(22474*32, 32); -- C10
- when "0001" => phase_delta <= to_unsigned(23810*32, 32); -- C10#
- when "0010" => phase_delta <= to_unsigned(25225*32, 32); -- D10
- when "0011" => phase_delta <= to_unsigned(26726*32, 32); -- D10#
- when "0100" => phase_delta <= to_unsigned(28315*32, 32); -- E10
- when "0101" => phase_delta <= to_unsigned(29999*32, 32); -- F10
- when "0110" => phase_delta <= to_unsigned(31782*32, 32); -- F10#
- when "0111" => phase_delta <= to_unsigned(33673*32, 32); -- G10
- when "1000" => phase_delta <= to_unsigned(35674*32, 32); -- G10#
- when "1001" => phase_delta <= to_unsigned(37796*32, 32); -- A10
- when "1010" => phase_delta <= to_unsigned(40043*32, 32); -- A10#
- when "1011" => phase_delta <= to_unsigned(42424*32, 32); -- B10
- when others => phase_delta <= to_unsigned(0, 32); -- Should never happen
- end case;
- end process;
+ phase_delta_32(11 downto 0) <= phase_delta;
process (clk)
begin
if (rising_edge(clk)) then
- phase_accumulator <= phase_accumulator + (phase_delta srl (10 - to_integer(octave)));
+ phase_accumulator <= phase_accumulator + (phase_delta_32 sll (to_integer(octave)));
end if;
end process;
View
95 mdsynth.srcs/sources_1/new/pitch_to_freq.vhd
@@ -0,0 +1,95 @@
+-- MD-Synthesizer
+--
+-- Author: Daniel Cliche (dcliche@meldora.com)
+-- Copyright (c) 2011, Meldora Inc. All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+-- * Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- * Redistributions in binary form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+-- * Neither the name of Meldora Inc. nor the
+-- names of its contributors may be used to endorse or promote products
+-- derived from this software without specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+-- DISCLAIMED. IN NO EVENT SHALL MELDORA INC. BE LIABLE FOR ANY
+-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+--
+-- MIDI-compatible pitch to NCO-compatible frequency with phase delta and octave
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity pitch_to_freq is
+ port ( pitch: in unsigned(6 downto 0); -- 60 = C4
+ phase_delta: out unsigned(11 downto 0);
+ octave: out unsigned(3 downto 0));
+end pitch_to_freq;
+
+architecture pitch_to_freq_arch of pitch_to_freq is
+
+component div_by_12 is
+ port ( numerator : in unsigned(6 downto 0);
+ quotient : out unsigned(3 downto 0);
+ remain : out unsigned(3 downto 0));
+end component;
+
+signal note: unsigned(3 downto 0);
+signal toggle: std_logic := '0';
+
+begin
+ div0: div_by_12 port map (numerator => pitch, quotient => octave, remain => note);
+
+ -- pitch 69 (A4) will give the following: octave=5, note=9
+ -- The desired frequencies for octave 5 are the following:
+ -- note freq (Hz)
+ -- 0 261.63 (C4)
+ -- 1 277.18
+ -- 2 293.66
+ -- 3 311.13
+ -- 4 329.63
+ -- 5 349.23
+ -- 6 369.99
+ -- 7 392.00
+ -- 8 415.30
+ -- 9 440.00 (A4)
+ -- 10 466.16
+ -- 11 493.88
+
+ -- The frequency given to NCO is the following:
+ -- freq = (50E6 * (phase_delta * 2^octave)) / 2^32
+ -- phase_delta = freq * 2^32 / (50E6 * 2^octave)
+
+ process (note)
+ begin
+ case note is
+ when "0000" => phase_delta <= to_unsigned(702, 12); -- C4
+ when "0001" => phase_delta <= to_unsigned(744, 12); -- C4#
+ when "0010" => phase_delta <= to_unsigned(788, 12); -- D4
+ when "0011" => phase_delta <= to_unsigned(835, 12); -- D4#
+ when "0100" => phase_delta <= to_unsigned(885, 12); -- E4
+ when "0101" => phase_delta <= to_unsigned(937, 12); -- F4
+ when "0110" => phase_delta <= to_unsigned(993, 12); -- F4#
+ when "0111" => phase_delta <= to_unsigned(1052, 12); -- G4
+ when "1000" => phase_delta <= to_unsigned(1115, 12); -- G4#
+ when "1001" => phase_delta <= to_unsigned(1181, 12); -- A4
+ when "1010" => phase_delta <= to_unsigned(1251, 12); -- A4#
+ when "1011" => phase_delta <= to_unsigned(1326, 12); -- B4
+ when others => phase_delta <= to_unsigned(0, 12); -- Should never happen
+ end case;
+ end process;
+
+end pitch_to_freq_arch;
View
137 planAhead.jou
@@ -0,0 +1,137 @@
+#-----------------------------------------------------------
+# PlanAhead v13.1
+# Build 117799 by hdbuild on Thu Feb 17 11:38:00 PST 2011
+# Start of session at: Sat Jun 11 14:54:11 2011
+# Process ID: 2656
+# Log file: C:/Users/dev/Xilinx/mdsynth/planAhead.log
+# Journal file: C:/Users/dev/Xilinx/mdsynth/planAhead.jou
+#-----------------------------------------------------------
+start_gui -project {C:\Users\dev\Xilinx\mdsynth\mdsynth.ppr}
+open_project {C:\Users\dev\Xilinx\mdsynth\mdsynth.ppr}
+reset_run -run synth_1
+launch_runs synth_1
+set_property add_step {} [get_runs impl_1]
+launch_runs impl_1
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs impl_1
+launch_impact
+launch_impact
+launch_impact
+close [ open {C:\Users\dev\Xilinx\mdsynth\mdsynth.srcs\sources_1\new\pitch_to_freq.vhd} w ]
+add_files {C:\Users\dev\Xilinx\mdsynth\mdsynth.srcs\sources_1\new\pitch_to_freq.vhd}
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+set_property add_step {} [get_runs impl_1]
+launch_runs impl_1
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs impl_1
+launch_impact
+reset_run -run synth_1
+launch_runs synth_1
+set_property add_step {} [get_runs impl_1]
+launch_runs impl_1
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs impl_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+set_property add_step {} [get_runs impl_1]
+launch_runs impl_1
+open_rtl_design -name rtl_1
+open_rtl_design -name rtl_1
+open_rtl_design -name rtl_1
+open_rtl_design -name rtl_1
+reset_run -run synth_1
+launch_runs synth_1
+launch_runs impl_1
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs impl_1
+launch_isim -simset sim_1 -mode behavioral
+launch_isim -simset sim_1 -mode behavioral
+reset_run -run synth_1
+launch_runs synth_1
+set_property add_step {} [get_runs impl_1]
+launch_runs impl_1
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs impl_1
+close_design
+open_impl_design
+open_rtl_design -name rtl_1
+open_rtl_design -name rtl_1
+refresh_design
+reset_run -run synth_1
+launch_runs synth_1
+set_property add_step {} [get_runs impl_1]
+launch_runs impl_1
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs impl_1
+reset_run -run synth_1
+launch_runs synth_1
+set_property add_step {} [get_runs impl_1]
+launch_runs impl_1
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs impl_1
+reset_run -run synth_1
+launch_runs synth_1
+refresh_design
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+set_property add_step {} [get_runs impl_1]
+launch_runs impl_1
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs impl_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+set_property add_step {} [get_runs impl_1]
+launch_runs impl_1
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs impl_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+set_property add_step {} [get_runs impl_1]
+launch_runs impl_1
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs impl_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+reset_run -run synth_1
+launch_runs synth_1
+set_property add_step {} [get_runs impl_1]
+launch_runs impl_1
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs impl_1
+current_design impl_1
+close_design
+open_impl_design
+exit

No commit comments for this range

Something went wrong with that request. Please try again.