Setup enviroment
$ make setup
Make Build fulladder example and testbench.
make
Do GTK wave.
make sim
Make svg file to view netlist.
make netlist
Figure 001. fulladder
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Make verilog descripted hardware module with testbench and generate RTL Diagram.
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deepbooks/make-verilog-tb-rtl
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Make verilog descripted hardware module with testbench and generate RTL Diagram.
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