{"payload":{"header_redesign_enabled":false,"results":[{"id":"416079245","archived":false,"color":"#b2b7f8","followers":2,"has_funding_file":false,"hl_name":"dgarci23/risc-v-32","hl_trunc_description":"32-bit processor with a RISC-V ISA. Designed in Verilog to be compatible with the DE2-115 FPGA. ","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":416079245,"name":"risc-v-32","owner_id":68306899,"owner_login":"dgarci23","updated_at":"2023-01-19T18:27:47.872Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":80,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Adgarci23%252Frisc-v-32%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/dgarci23/risc-v-32/star":{"post":"ug4xZU9s3xPCmcqlHH6Md90hvnTzYl6_Gooicrr0wxh3FkMG_ERROCCDLttVn86eVTv2GOZoiKHh2akyPTmRug"},"/dgarci23/risc-v-32/unstar":{"post":"qEjyieJEpBsCLaJqYobKwZx9p_cjM0wvKHdVHUZFnJKKD9xTQqNWGgLZF2hrNl1QX-WR_PLtswpZD8nzTYLsCg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"yyq60QwaQSUzbVTG4diTAKVRPVwuXGEquNd2UwMZJ38Mr-3ptoxewYZinVHaAEWSIxeJgegqz6mCmdoF-FGq2A"}}},"title":"Repository search results"}