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vivado_186684.backup.jou
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vivado_186684.backup.jou
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#-----------------------------------------------------------
# Vivado v2014.3 (64-bit)
# SW Build 1018564 on Mon Sep 15 19:04:16 MDT 2014
# IP Build 1018438 on Mon Sep 15 16:10:11 MDT 2014
# Start of session at: Tue Sep 23 17:33:00 2014
# Process ID: 86952
# Log file: C:/PROJECT_FOR_RELEASE/AC701_100Mhz_64kb/ac701_lwip_design/ac701_lwip_design/project_1/vivado.log
# Journal file: C:/PROJECT_FOR_RELEASE/AC701_100Mhz_64kb/ac701_lwip_design/ac701_lwip_design/project_1\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/PROJECT_FOR_RELEASE/AC701_100Mhz_64kb/ac701_lwip_design/ac701_lwip_design/project_1/project_1.xpr
report_ip_status -name ip_status
upgrade_ip [get_ips {design_1_lmb_bram_0 design_1_axi_ethernet_0_0 design_1_dlmb_bram_if_cntlr_0 design_1_ilmb_bram_if_cntlr_1 design_1_microblaze_0_0 design_1_proc_sys_reset_1_0 design_1_mig_7series_0_0 design_1_axi_uartlite_0_0 design_1_microblaze_0_axi_periph_0 design_1_microblaze_0_axi_intc_0 design_1_axi_timer_0_0 design_1_axi_mem_intercon_1 design_1_clk_wiz_0_0 design_1_axi_ethernet_0_dma_0 design_1_blk_mem_gen_0_1 design_1_axi_bram_ctrl_0_0 design_1_mdm_1_0}]
assign_bd_address [get_bd_addr_segs {axi_ethernet_0/s_axi/Reg }]
set_property offset 0x44A00000 [get_bd_addr_segs {microblaze_0/Data/SEG_axi_ethernet_0_Reg}]
startgroup
set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF} CONFIG.C_ICACHE_VICTIMS {4} CONFIG.C_ICACHE_STREAMS {1} CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF} CONFIG.C_DCACHE_USE_WRITEBACK {1} CONFIG.C_DCACHE_VICTIMS {4}] [get_bd_cells microblaze_0]
endgroup
startgroup
set_property -dict [list CONFIG.C_DCACHE_VICTIMS {4}] [get_bd_cells microblaze_0]
endgroup
startgroup
set_property -dict [list CONFIG.c_mm2s_burst_size {32} CONFIG.c_s2mm_burst_size {32}] [get_bd_cells axi_ethernet_0_dma]
endgroup
startgroup
set_property -dict [list CONFIG.STRATEGY {2} CONFIG.S00_HAS_DATA_FIFO {2} CONFIG.S01_HAS_DATA_FIFO {2} CONFIG.S02_HAS_DATA_FIFO {2} CONFIG.S03_HAS_DATA_FIFO {2} CONFIG.S04_HAS_DATA_FIFO {2}] [get_bd_cells axi_mem_intercon]
endgroup
validate_bd_design
save_bd_design
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
open_run impl_1
file mkdir C:/PROJECT_FOR_RELEASE/AC701_100Mhz_64kb/ac701_lwip_design/ac701_lwip_design/project_1/project_1.sdk
file copy -force C:/PROJECT_FOR_RELEASE/AC701_100Mhz_64kb/ac701_lwip_design/ac701_lwip_design/project_1/project_1.runs/impl_1/design_1_wrapper.sysdef C:/PROJECT_FOR_RELEASE/AC701_100Mhz_64kb/ac701_lwip_design/ac701_lwip_design/project_1/project_1.sdk/design_1_wrapper.hdf
launch_sdk -workspace C:/PROJECT_FOR_RELEASE/AC701_100Mhz_64kb/ac701_lwip_design/ac701_lwip_design/project_1/project_1.sdk -hwspec C:/PROJECT_FOR_RELEASE/AC701_100Mhz_64kb/ac701_lwip_design/ac701_lwip_design/project_1/project_1.sdk/design_1_wrapper.hdf