diff --git a/src/verilog/verilog_expr.h b/src/verilog/verilog_expr.h
index 02fb0964d..9f7b197c3 100644
--- a/src/verilog/verilog_expr.h
+++ b/src/verilog/verilog_expr.h
@@ -854,6 +854,18 @@ class verilog_inst_baset : public verilog_module_itemt
       return operands();
     }
 
+    bool positional_port_connections() const
+    {
+      return !named_port_connections();
+    }
+
+    bool named_port_connections() const
+    {
+      auto &connections = this->connections();
+      return connections.empty() ||
+             connections.front().id() == ID_named_port_connection;
+    }
+
   protected:
     using exprt::operands;
   };
diff --git a/src/verilog/verilog_synthesis.cpp b/src/verilog/verilog_synthesis.cpp
index 61416ae2d..23378937d 100644
--- a/src/verilog/verilog_synthesis.cpp
+++ b/src/verilog/verilog_synthesis.cpp
@@ -1419,7 +1419,7 @@ void verilog_synthesist::instantiate_ports(
 
   // named port connection?
 
-  if(inst.connections().front().id() == ID_named_port_connection)
+  if(inst.named_port_connections())
   {
     const irept::subt &ports = symbol.type.find(ID_ports).get_sub();
 
diff --git a/src/verilog/verilog_typecheck.cpp b/src/verilog/verilog_typecheck.cpp
index 904ccc6a3..e171ffea3 100644
--- a/src/verilog/verilog_typecheck.cpp
+++ b/src/verilog/verilog_typecheck.cpp
@@ -110,9 +110,7 @@ void verilog_typecheckt::typecheck_port_connections(
   }
 
   // named port connection?
-  if(
-    inst.connections().empty() ||
-    inst.connections().front().id() == ID_named_port_connection)
+  if(inst.named_port_connections())
   {
     // We don't require that all ports are connected.