From a9a9214c69c268b73ec16359c548b73030f27ae2 Mon Sep 17 00:00:00 2001 From: Daniel Kroening Date: Mon, 15 Sep 2025 18:58:42 -0700 Subject: [PATCH] Verilog: helper methods for port connections Port connections of a module instance can be named or positional. This adds two helper methods to distinguish these two cases. --- src/verilog/verilog_expr.h | 12 ++++++++++++ src/verilog/verilog_synthesis.cpp | 2 +- src/verilog/verilog_typecheck.cpp | 4 +--- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/src/verilog/verilog_expr.h b/src/verilog/verilog_expr.h index 02fb0964d..9f7b197c3 100644 --- a/src/verilog/verilog_expr.h +++ b/src/verilog/verilog_expr.h @@ -854,6 +854,18 @@ class verilog_inst_baset : public verilog_module_itemt return operands(); } + bool positional_port_connections() const + { + return !named_port_connections(); + } + + bool named_port_connections() const + { + auto &connections = this->connections(); + return connections.empty() || + connections.front().id() == ID_named_port_connection; + } + protected: using exprt::operands; }; diff --git a/src/verilog/verilog_synthesis.cpp b/src/verilog/verilog_synthesis.cpp index 61416ae2d..23378937d 100644 --- a/src/verilog/verilog_synthesis.cpp +++ b/src/verilog/verilog_synthesis.cpp @@ -1419,7 +1419,7 @@ void verilog_synthesist::instantiate_ports( // named port connection? - if(inst.connections().front().id() == ID_named_port_connection) + if(inst.named_port_connections()) { const irept::subt &ports = symbol.type.find(ID_ports).get_sub(); diff --git a/src/verilog/verilog_typecheck.cpp b/src/verilog/verilog_typecheck.cpp index 904ccc6a3..e171ffea3 100644 --- a/src/verilog/verilog_typecheck.cpp +++ b/src/verilog/verilog_typecheck.cpp @@ -110,9 +110,7 @@ void verilog_typecheckt::typecheck_port_connections( } // named port connection? - if( - inst.connections().empty() || - inst.connections().front().id() == ID_named_port_connection) + if(inst.named_port_connections()) { // We don't require that all ports are connected.