diff --git a/regression/verilog/arrays/unpacked_array_concatenation1.desc b/regression/verilog/arrays/unpacked_array_concatenation1.desc
new file mode 100644
index 000000000..fb3c07002
--- /dev/null
+++ b/regression/verilog/arrays/unpacked_array_concatenation1.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+unpacked_array_concatenation1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+This yields a type checking error.
diff --git a/regression/verilog/arrays/unpacked_array_concatenation1.sv b/regression/verilog/arrays/unpacked_array_concatenation1.sv
new file mode 100644
index 000000000..147a8e278
--- /dev/null
+++ b/regression/verilog/arrays/unpacked_array_concatenation1.sv
@@ -0,0 +1,11 @@
+module main;
+
+  // 1800-2017 10.10 Unpacked array concatenation
+  byte my_bytes [1:4] = { 1, 2, 3, 4 };
+
+  assert final(my_bytes[1] == 1);
+  assert final(my_bytes[2] == 2);
+  assert final(my_bytes[3] == 3);
+  assert final(my_bytes[4] == 4);
+
+endmodule