From 11d1dc075250d3e36f4de7d1465c7d96511f8e47 Mon Sep 17 00:00:00 2001 From: Daniel Kroening Date: Thu, 16 Oct 2025 08:38:18 -0700 Subject: [PATCH] Verilog: extend shl4 test This adds a nested case to the test for the expression evaluation context. --- regression/verilog/expressions/shl4.sv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/regression/verilog/expressions/shl4.sv b/regression/verilog/expressions/shl4.sv index 0c9e27c95..383d227eb 100644 --- a/regression/verilog/expressions/shl4.sv +++ b/regression/verilog/expressions/shl4.sv @@ -9,4 +9,7 @@ module main; assert final (1'b1 << 6 === 64); assert final (1'b1 << 6 === 1'b0); + // The shift will have 16 bits! + initial assert(8'b0 + (1'sb1 << 15) === 16'b1000_0000_0000_0000); + endmodule