diff --git a/regression/verilog/expressions/equality4.desc b/regression/verilog/expressions/equality4.desc
new file mode 100644
index 000000000..876c1fb1d
--- /dev/null
+++ b/regression/verilog/expressions/equality4.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+equality4.v
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+zero_extend doesn't work for four-valued operands.
diff --git a/regression/verilog/expressions/equality4.sv b/regression/verilog/expressions/equality4.sv
new file mode 100644
index 000000000..397b52ae0
--- /dev/null
+++ b/regression/verilog/expressions/equality4.sv
@@ -0,0 +1,11 @@
+module main;
+
+  // The two operands are zero-extended to 8 bits.
+  initial assert((2'b10 + 1'sbx) === 8'bxxxxxxxx);
+  initial assert((2'b10 | 1'sbx) === 8'b0000001x);
+
+  // The two operands are sign-extended to 8 bits.
+  initial assert((2'sb10 + 1'sbx) === 8'sbxxxxxxxx);
+  initial assert((2'sb10 | 1'sbx) === 8'sb1111111x);
+
+endmodule